Abstract: SR-IOV (single root IO virtualization) capable PCIe devices can implement virtual functions (VFs) that are assigned to VMs running on a host machine, thereby speeding IO operation by writing directly to the VMs' memory while bypassing the hypervisor managing the VMs. As such, VFs thwart the dirty page tracking that hypervisors use to minimize VM downtime when the VM is migrated between hosts. The SR-IOV PCIe devices can help resolve this problem by maintaining dirty page tracking data for VMs running on the host machine. The SR-IOV PCIe devices bypassing the hypervisor while writing into a memory page of the VM can set the dirty page tracking data to indicate the memory pages that are dirty (i.e., written to by the VF), and can provide access to the dirty page tracking data. The hypervisor can thereby obtain and use the dirty page tracking data.

Abstract: A system includes a host and at least two Bluetooth controllers. The host is configured to execute a Bluetooth protocol stack. The at least two Bluetooth controllers are communicatively coupled to the host. Each Bluetooth controller is configured to wirelessly communicate with at least one respective external device.

Abstract: A microelectronic device comprises a stack structure, first dielectric-filled trenches extending vertically through the stack structure, and at least one second dielectric-filled trench intersecting the first dielectric-filled trenches. The stack structure comprises a vertically alternating sequence of conductive material and insulative material arranged in tiers. The first dielectric-filled trenches divide the stack structure into blocks and extend horizontally in a first direction. At least one second dielectric-filled trench extends horizontally in a second direction orthogonal to the first direction. At least one second dielectric-filled trench has boundaries defined by at least one staircase structure having steps defined by horizontal ends of the tiers in the first direction. Memory devices and electronic systems are also described.

Abstract: A method of forming a microelectronic device comprises forming a stack structure over a source structure, forming pillar structures vertically extending through the stack structure, and forming at least one trench vertically extending through the stack structure. The at least one trench defines at least one stadium structure comprising opposing stair step structures having steps comprising horizontal ends of tiers. Additional trenches may be formed to vertically extend through the stack structure, and at least one further trench may be formed to vertically extend through the stack structure. The at least one further trench defines at least one additional stadium structure comprising additional opposing stair step structures having additional steps comprising additional horizontal ends of the tiers. A dielectric material may be formed within the at least one trench, the additional trenches, and the at least one further trench. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Methods, systems, and devices for isolation regions within a memory die are described. During fabrication, memory pillars may be formed through a stack of material in a plurality regions of a memory die. In some cases, a first plurality of trenches extending in a first direction and a second plurality of trenches extending in a second direction may be formed through the stack of material (e.g., interposed between the plurality of regions). Additionally or alternatively, first voids may be formed via the first plurality of trenches, and a dielectric material may be deposited in the first voids and the first plurality of trenches, forming first isolation regions. Then, second voids may be formed via the second plurality of trenches, and a dielectric material may be deposited in the second voids and the second plurality of trenches, forming second isolation regions.

Abstract: Methods, systems, and devices for lateral etch stops for access line formation in a memory die are described. A memory die may be formed with isolation regions that provide an etch stop to limit the extent of voids formed by removing a sacrificial material between layers of a dielectric region. For example, first trenches may be formed through a stack of alternating layers of a dielectric material and a sacrificial material, in which one or more materials may formed. Second trenches may be formed between a first trench and an array portion of the memory die, or between pairs of the first trenches, which may support the removal of at least a portion of the sacrificial material to form voids for access line formation. However, the materials formed in the first trenches may provide a boundary, or a restriction zone, that limits an extent of the material removal operation.

Abstract: A memory device can include a semiconductor substrate having a plurality of active semiconductor devices. The memory device can include a plurality of metallization layers disposed over the semiconductor substrate, where each of the plurality of metallization layers is separated from adjacent metallization layers by an interlayer dielectric. The memory device also includes a dummy metal fill disposed in a metallization layer. The dummy metal fill can be connected to a discharge path for dissipating a charge build up in the dummy metal fill to minimize antenna effects. In some embodiments, the discharge path can include the semiconductor substrate, which can be an electrical drain. The antenna protected dummy metal fill ensures is configured such that any accumulated charge during the fabrication process is discharged to the electric drain.

Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

Abstract: Virtual functions (VFs) running on SR-IOV (single root IO virtualization) capable PCIe devices can migrate in association with VMs using the VFs. A SR-IOV capable PCIe device installed in a host computer can implement the VFs. A VM running on the host and associated with the VF can use the VF to obtain a service such as network communications or access to a NAS device. Migrating the VF in association with the VM can include halting the VM in a VM state on the host, halting the VF in a PCIe state and then obtaining a PCIe state data, restarting the VF in the PCIe state on a second PCIe device of a second host based on the PCIe state data, and restarting the VM in the VM state on the second host, wherein the VM is configured to use the VF on the second PCIe device.

Abstract: Embodiments of the disclosure provide a method and device for efficiently reducing dimensions of an image frame by an electronic device. The method includes: receiving the image frame; transforming the image frame from a spatial domain comprising a first plurality of channels to a non-spatial domain comprising a second plurality of channels, where a number of the second plurality of channels is greater than a number of the first plurality of channels; removing channels comprising irrelevant information from among the second plurality of channels using an AI engine to generate a low-resolution image frame in the non-spatial domain; and providing the low-resolution image frame to a neural network for a faster and accurate inference of the image frame.

Abstract: The present disclosure relates to methods, systems, and non-transitory computer-readable media for determining a cognitive, action-selection bias of a user that influences how the user will select a sequence of digital actions for execution of a task. For example, the disclosed systems can identify, from a digital behavior log of a user, a set of digital action sequences that correspond to a set of sessions for a task previously executed by the user. The disclosed systems can utilize a machine learning model to analyze the set of sessions to generate session weights. The session weights can correspond to an action-selection bias that indicates an extent to which a future session for the task executed by the user is predicted to be influenced by the set of sessions. The disclosed systems can provide a visual indication of the action-selection bias of the user for display on a graphical user interface.

Abstract: A method of forming a microelectronic device comprises forming a stack structure over a source structure, forming pillar structures vertically extending through the stack structure, and forming at least one trench vertically extending through the stack structure. The at least one trench defines at least one stadium structure comprising opposing stair step structures having steps comprising horizontal ends of tiers. Additional trenches may be formed to vertically extend through the stack structure, and at least one further trench may be formed to vertically extend through the stack structure. The at least one further trench defines at least one additional stadium structure comprising additional opposing stair step structures having additional steps comprising additional horizontal ends of the tiers. A dielectric material may be formed within the at least one trench, the additional trenches, and the at least one further trench. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Various embodiments of the disclosure disclose a method for quantizing a Deep Neural Network (DNN) model in an electronic device. The method includes: estimating, by the electronic device, an activation range of each layer of the DNN model using self-generated data (e.g. retro image, audio, video, etc.) and/or a sensitive index of each layer of the DNN model; quantizing, by the electronic device, the DNN model based on the activation range and/or the sensitive index; and allocating, by the electronic device, a dynamic bit precision for each channel of each layer of the DNN model to quantize the DNN model.

Abstract: Semiconductor devices with slotted vias, and associated systems and methods, are disclosed herein. In one embodiment, a routing region of the semiconductor device includes a set of slotted vias arranged in a non-orthogonal array pattern. Further, patterns of metal lines associated with the set of slotted vias are drawn to align and/or overlap with the slotted vias. As a result, the metal lines may include zig-zag patterns within the routing region. Further, edges of the slotted vias may have a staircase pattern with sets of horizontal and vertical line segments such that a combination of the horizontal and vertical line segments can orient the slotted vias in a non-orthogonal direction.

Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

Abstract: SR-IOV (single root IO virtualization) capable PCIe devices can implement virtual functions (VFs) that are assigned to VMs running on a host machine, thereby speeding IO operation by writing directly to the VMs' memory while bypassing the hypervisor managing the VMs. As such, VFs thwart the dirty page tracking that hypervisors use to minimize VM downtime when the VM is migrated between hosts. The SR-IOV PCIe devices can help resolve this problem by maintaining dirty page tracking data for VMs running on the host machine. The SR-IOV PCIe devices bypassing the hypervisor while writing into a memory page of the VM can set the dirty page tracking data to indicate the memory pages that are dirty (i.e., written to by the VF), and can provide access to the dirty page tracking data. The hypervisor can thereby obtain and use the dirty page tracking data.

Abstract: Semiconductor devices with slotted vias, and associated systems and methods, are disclosed herein. In one embodiment, a routing region of the semiconductor device includes a set of slotted vias arranged in a non-orthogonal array pattern. Further, patterns of metal lines associated with the set of slotted vias are drawn to align and/or overlap with the slotted vias. As a result, the metal lines may include zig-zag patterns within the routing region. Further, edges of the slotted vias may have a staircase pattern with sets of horizontal and vertical line segments such that a combination of the horizontal and vertical line segments can orient the slotted vias in a non-orthogonal direction.

Abstract: Load balancing of NVMe targets based on real time metrics can be obtained for NAS appliances mirroring a namespace by assigning the NAS appliances to service sets that include an active load balancing set, a monitored inactive set, and an out of service set. Storage performance metrics of the NAS appliances can be tracked by monitoring IO operations for accessing a NAS mirroring the namespace in a non-volatile memory. Based on the storage metrics, NAS appliances can be moved from one of the service sets to another. Dummy IO operations can be used to track the storage performance metrics of monitored inactive NAS appliances such that a monitored inactive NAS may be moved to the active load balancing set when certain performance constraints are met.

Abstract: Load balancing of NVMe targets based on real time metrics can be obtained for NAS appliances mirroring a namespace by assigning the NAS appliances to service sets that include an active load balancing set, a monitored inactive set, and an out of service set. Storage performance metrics of the NAS appliances can be tracked by monitoring IO operations for accessing a NAS mirroring the namespace in a non-volatile memory. Based on the storage metrics, NAS appliances can be moved from one of the service sets to another. Dummy IO operations can be used to track the storage performance metrics of monitored inactive NAS appliances such that a monitored inactive NAS may be moved to the active load balancing set when certain performance constraints are met.