Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: There is disclosed in one example a computer apparatus, including: a hardware platform including a central processor unit (CPU) and a memory; and instructions encoded within the memory to instruct the CPU to: enumerate a plurality of running processes, and associate resource demands with the running processes; predict a resource starvation condition for at least one process; rank the plurality of running processes according to a dynamic ranking algorithm, wherein the ranking algorithm includes user engagement as an input for ranking a process; and according to the ranking and a safeguard algorithm, deallocate resources from a process ranked lower than the at least one process and assign the deallocated resources to the at least one process to mitigate the predicted resource starvation condition.

Abstract: A 3D printer includes a nozzle configured to jet a drop of liquid metal therethrough. The 3D printer also includes a light source configured to illuminate the drop with a pulse of light. A duration of the pulse of light is from about 0.0001 seconds to about 0.1 seconds. The 3D printer also includes a camera configured to capture an image, video, or both of the drop. The 3D printer also includes a computing system configured to detect the drop in the image, the video, or both. The computing system is also configured to characterize the drop after the drop is detected. Characterizing the drop includes determining a size of the drop, a location of the drop, or both in the image, the video, or both.

Abstract: Methods, systems, and devices for wireless communications are described. A distributed unit (DU) component/function of a base station may determine, for one or more radio units associated with the distributed unit, one or more sampling metrics associated with signal combining operations at the radio units. The DU may select, based at least in part on the one or more sampling metrics, a combining scheme to use for the signal combining operations. The DU may provide an indication of the selected combining scheme to at least one radio unit of the one or more radio units.

Abstract: Provided is a method for generating Augmented Reality (AR) content that includes: receiving a plurality of image frames of at least one scene captured by a plurality of participant devices in an AR or a Virtual Reality (VR) environment; storing the plurality of image frames and metadata associated with the plurality of image frames, in a database; receiving an AR content generation request to generate an AR content view of a user in the AR/VR environment, the AR content generation request including an identifier (ID) of the user and information of the at least one scene; retrieving a set of image frames from a plurality of stored image frames in the database based on the ID of the user, the information of the at least one scene, and metadata associated with the set of image frames, the set of images including the user in the at least one scene in the AR/VR environment; generating the AR content view of the user by combining the set of image frames retrieved from the database, based on the metadata associated

Abstract: This disclosure describes systems, methods, and computer-readable media related to mobile device purchase flows. In some embodiments, a mobile device may obtain a uniform resource identifier (URI). The mobile device may launch a browser based at least in part on the URI. The mobile device may submit a first set of data to a server based at least in part on the URI and receive a re-direct URI. The mobile device may launch an application in response to receiving the re-direct URI from the server, wherein the application submits a second set of data to the server. The mobile device may facilitate completion of a transaction by the application based at least in part on matching the first set of data and the second set of data at the server.

Abstract: Certain aspects of the present disclosure provide techniques for dynamic configuration of demodulation reference signals (DMRSs). A method that may be performed by a base station (BS) includes receiving one or more uplink signals from at least one user equipment (UE); estimating a Doppler shift associated with the one or more uplink signals; determining a density of reference signals (RSs) within a slot for the at least one UE based, at least in part, on the estimated Doppler shift associated with the one or more uplink signals; and transmitting information to the at least one UE indicating an allocation of RS resources for the UE, wherein the allocation of the RS resources is based on the density of the RSs for the at least one UE.

Abstract: Techniques described herein include frameworks and models for identifying, analyzing, and addressing hangs within distributed and heterogenous computing environments. A hang detection framework may model a distributed computing environment as a complex forest of interrelated requests. The hang detection framework may generate hang graphs based upon requests that are being processed and/or waited upon within the distributed environment. For example, a node within an acyclic graph may represent an execution entity that is currently processing one or more requests. Directed edges that connect one node to another may represent requests upon which an execution entity is waiting for another execution node to fulfill. The model may be used to isolate and address the root cause of hangs within the computing environment.

Abstract: Methods, systems, and devices for isolation regions within a memory die are described. During fabrication, memory pillars may be formed through a stack of material in a plurality regions of a memory die. In some cases, a first plurality of trenches extending in a first direction and a second plurality of trenches extending in a second direction may be formed through the stack of material (e.g., interposed between the plurality of regions). Additionally or alternatively, first voids may be formed via the first plurality of trenches, and a dielectric material may be deposited in the first voids and the first plurality of trenches, forming first isolation regions. Then, second voids may be formed via the second plurality of trenches, and a dielectric material may be deposited in the second voids and the second plurality of trenches, forming second isolation regions.

Abstract: Methods, systems, and devices for lateral etch stops for access line formation in a memory die are described. A memory die may be formed with isolation regions that provide an etch stop to limit the extent of voids formed by removing a sacrificial material between layers of a dielectric region. For example, first trenches may be formed through a stack of alternating layers of a dielectric material and a sacrificial material, in which one or more materials may formed. Second trenches may be formed between a first trench and an array portion of the memory die, or between pairs of the first trenches, which may support the removal of at least a portion of the sacrificial material to form voids for access line formation. However, the materials formed in the first trenches may provide a boundary, or a restriction zone, that limits an extent of the material removal operation.

Abstract: A memory device can include a semiconductor substrate having a plurality of active semiconductor devices. The memory device can include a plurality of metallization layers disposed over the semiconductor substrate, where each of the plurality of metallization layers is separated from adjacent metallization layers by an interlayer dielectric. The memory device also includes a dummy metal fill disposed in a metallization layer. The dummy metal fill can be connected to a discharge path for dissipating a charge build up in the dummy metal fill to minimize antenna effects. In some embodiments, the discharge path can include the semiconductor substrate, which can be an electrical drain. The antenna protected dummy metal fill ensures is configured such that any accumulated charge during the fabrication process is discharged to the electric drain.

Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

Abstract: Virtual functions (VFs) running on SR-IOV (single root IO virtualization) capable PCIe devices can migrate in association with VMs using the VFs. A SR-IOV capable PCIe device installed in a host computer can implement the VFs. A VM running on the host and associated with the VF can use the VF to obtain a service such as network communications or access to a NAS device. Migrating the VF in association with the VM can include halting the VM in a VM state on the host, halting the VF in a PCIe state and then obtaining a PCIe state data, restarting the VF in the PCIe state on a second PCIe device of a second host based on the PCIe state data, and restarting the VM in the VM state on the second host, wherein the VM is configured to use the VF on the second PCIe device.

Abstract: Embodiments of the disclosure provide a method and device for efficiently reducing dimensions of an image frame by an electronic device. The method includes: receiving the image frame; transforming the image frame from a spatial domain comprising a first plurality of channels to a non-spatial domain comprising a second plurality of channels, where a number of the second plurality of channels is greater than a number of the first plurality of channels; removing channels comprising irrelevant information from among the second plurality of channels using an AI engine to generate a low-resolution image frame in the non-spatial domain; and providing the low-resolution image frame to a neural network for a faster and accurate inference of the image frame.

Abstract: The present disclosure relates to methods, systems, and non-transitory computer-readable media for determining a cognitive, action-selection bias of a user that influences how the user will select a sequence of digital actions for execution of a task. For example, the disclosed systems can identify, from a digital behavior log of a user, a set of digital action sequences that correspond to a set of sessions for a task previously executed by the user. The disclosed systems can utilize a machine learning model to analyze the set of sessions to generate session weights. The session weights can correspond to an action-selection bias that indicates an extent to which a future session for the task executed by the user is predicted to be influenced by the set of sessions. The disclosed systems can provide a visual indication of the action-selection bias of the user for display on a graphical user interface.

Abstract: Various embodiments of the disclosure disclose a method for quantizing a Deep Neural Network (DNN) model in an electronic device. The method includes: estimating, by the electronic device, an activation range of each layer of the DNN model using self-generated data (e.g. retro image, audio, video, etc.) and/or a sensitive index of each layer of the DNN model; quantizing, by the electronic device, the DNN model based on the activation range and/or the sensitive index; and allocating, by the electronic device, a dynamic bit precision for each channel of each layer of the DNN model to quantize the DNN model.

Abstract: A method of forming a microelectronic device comprises forming a stack structure over a source structure, forming pillar structures vertically extending through the stack structure, and forming at least one trench vertically extending through the stack structure. The at least one trench defines at least one stadium structure comprising opposing stair step structures having steps comprising horizontal ends of tiers. Additional trenches may be formed to vertically extend through the stack structure, and at least one further trench may be formed to vertically extend through the stack structure. The at least one further trench defines at least one additional stadium structure comprising additional opposing stair step structures having additional steps comprising additional horizontal ends of the tiers. A dielectric material may be formed within the at least one trench, the additional trenches, and the at least one further trench. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Semiconductor devices with slotted vias, and associated systems and methods, are disclosed herein. In one embodiment, a routing region of the semiconductor device includes a set of slotted vias arranged in a non-orthogonal array pattern. Further, patterns of metal lines associated with the set of slotted vias are drawn to align and/or overlap with the slotted vias. As a result, the metal lines may include zig-zag patterns within the routing region. Further, edges of the slotted vias may have a staircase pattern with sets of horizontal and vertical line segments such that a combination of the horizontal and vertical line segments can orient the slotted vias in a non-orthogonal direction.

Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.