Patents by Inventor Rajabali Koduri

Rajabali Koduri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200211970
    Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Wilfred GOMES, Mark BOHR, Rajabali KODURI, Leonard NEIBERG, Altug KOKER, Swaminathan SIVAKUMAR
  • Patent number: 9201608
    Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: December 1, 2015
    Assignee: Apple Inc.
    Inventors: Ian C. Hendry, Rajabali Koduri, Jeffry E. Gonion
  • Patent number: 9128849
    Abstract: Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: September 8, 2015
    Assignee: Apple Inc.
    Inventors: Ian Hendry, Rajabali Koduri
  • Patent number: 9009383
    Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: April 14, 2015
    Assignee: Apple Inc.
    Inventors: Ian C. Hendry, Rajabali Koduri, Jeffry E. Gonion
  • Publication number: 20140331020
    Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.
    Type: Application
    Filed: July 14, 2014
    Publication date: November 6, 2014
    Inventors: Ian C. Hendry, Rajabali Koduri, Jeffry E. Gonion
  • Publication number: 20140325173
    Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.
    Type: Application
    Filed: July 15, 2014
    Publication date: October 30, 2014
    Inventors: Ian C. Hendry, Rajabali Koduri, Jeffry E. Gonion
  • Patent number: 8799553
    Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: August 5, 2014
    Assignee: Apple Inc.
    Inventors: Ian Hendry, Rajabali Koduri, Jeffry Gonion
  • Publication number: 20110252180
    Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active.
    Type: Application
    Filed: September 30, 2010
    Publication date: October 13, 2011
    Applicant: APPLE INC.
    Inventors: Ian Hendry, Rajabali Koduri, Jeffry Gonion
  • Publication number: 20110252200
    Abstract: Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 13, 2011
    Applicant: APPLE INC.
    Inventors: Ian Hendry, Rajabali Koduri
  • Publication number: 20070257935
    Abstract: A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.
    Type: Application
    Filed: May 8, 2006
    Publication date: November 8, 2007
    Applicant: ATI Technologies Inc.
    Inventors: Rajabali Koduri, Gordon Elder, Jeffrey Golds