Patents by Inventor Rajagopal Ananthanarayanan

Rajagopal Ananthanarayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040221125
    Abstract: Various copy-on-write implementations for a computing environment are presented. One copy-on-write implementation includes employing a read mapping table to perform a first virtual block to physical block mapping for use in reading a block of data of a file to be copy-on-written from physical storage for modification; and employing a different, write mapping table to perform a second virtual block to physical block mapping for use in writing a modified block of the file data to physical storage, wherein copy-on-write of the block of data is achieved using a single write operation. In another implementation, a distributed copy-on-write of a file for a client server environment is presented. This distributed copy-on-write includes performing, by a first client, copy-on-write of at least one block of data of the file to be copy-on-written, and performing, by a second client, copy-on-write of at least one other block of data of the file, wherein multiple clients perform the copy-on-write of the file.
    Type: Application
    Filed: April 29, 2003
    Publication date: November 4, 2004
    Applicant: International Business Machines Corporation
    Inventors: Rajagopal Ananthanarayanan, Ralph A. Becker-Szendy, Robert M. Rees, Randal C. Burns, Darrell D.E. Long, Jujjuri Venkateswararao, David M. Wolfe, Jason C. Young
  • Publication number: 20040220931
    Abstract: A method and system for asserting a lock in a distributed file system is provided. All distributed locks have a lease for a limited time period, wherein the lease may be renewed periodically. A lock manager data structure is provided to maintain mode compatibility of locks granted to different client nodes for the same system object. The process of acquiring (60) or reasserting (140) a lock includes determining whether there are other valid locks in use, as well as whether a valid lock is operation in a conflicting or compatible mode with a requested lock (86, 166). A new lock lease maybe granted (120) and a lock lease which has expired may be reasserted (172) if a conflicting lease is not present.
    Type: Application
    Filed: April 29, 2003
    Publication date: November 4, 2004
    Inventors: D. Scott Guthridge, Rajagopal Ananthanarayanan, Ralph A. Becker-Szendy, Robert M. Rees
  • Patent number: 6766515
    Abstract: A system and a method of scheduling a plurality of threads from a multi-threaded program. A shared arena is provided in user memory, wherein the shared arena includes a register save area for each of the plurality of threads. A processor, when allocated to the application, executes the application's user-level scheduler and selects a user-level thread from a plurality of available threads, wherein the step of selecting includes the step of reading register context associated with the selected thread from one of the plurality of register save areas. In multikernel systems, kernels having access to an application's register save areas can execute preempted threads from that application with no kernel-to-kernel communication. Likewise, kernels having access to an application's user-level run queues can execute ready-to-run threads from that application with no kernel-to-kernel communication.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: July 20, 2004
    Assignee: Silicon Graphics, Inc.
    Inventors: Nawaf K. Bitar, Robert M. English, Rajagopal Ananthanarayanan
  • Patent number: 6714960
    Abstract: A precise earnings-based time-share scheduler schedules multiple jobs in a computer system by apportioning earnings, at scheduler ticks. Earnings are apportioned to jobs based on actual time a job spent in a queue requesting execution on a central processing unit (CPU) in the computer system between scheduler ticks and amounts of time jobs ran on the CPU between scheduler ticks. At the end of a time slice, a job is selected for execution on the processor based on earnings apportioned to each job.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: March 30, 2004
    Assignee: Silicon Graphics, Inc.
    Inventors: Nawaf K. Bitar, Robert M. English, Rajagopal Ananthanarayanan
  • Patent number: 6418460
    Abstract: A system and method for inexpensively detecting preempted execution entities such as threads without kernel involvement. In a computer system having a memory and one or more processors, a shared memory arena is formed in user space within the memory. A preempt bit vector is then formed within the shared memory arena such that the preempt bit vector is accessible to any of a plurality of execution entities running in user mode. The preempt bit vector includes a plurality of rbits, wherein each rbit is associated with one of the plurality of execution entities and wherein an rbit is marked whenever its associated execution entity is preempted. Detection of preempted threads then becomes a matter of reading, via program code executing in user mode on one of the plurality of processors, bits in the preempt bit vector to detect preempted execution entities.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: July 9, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: Nawaf K. Bitar, Robert M. English, Rajagopal Ananthanarayanan
  • Patent number: 5928322
    Abstract: A low-latency real-time dispatching scheme performed by the operating system of a general purpose multiprocessor system having N processors, assigns a priority to each of multiple real-time threads to be executed on the N processors. The multiple real-time threads include up to N top priority real-time threads, which are bound to a corresponding processor. The assigned priority of each bound real-time thread is the highest priority for being executed on its corresponding processor, and any other real-time thread being executed on the corresponding processor is preempted if the bound real-time thread becomes runnable.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: July 27, 1999
    Assignee: Silicon Graphics, Inc.
    Inventors: Nawaf K. Bitar, Rajagopal Ananthanarayanan, Robert M. English
  • Patent number: 5872963
    Abstract: A system and method for context switching between a first and a second execution entity (such as a thread) without having to enter into protected kernel mode. The system includes a memory and a plurality of processors, wherein each of the plurality of processors operates within both a user mode and a protected kernel mode and includes a program counter and a plurality N of registers. The first and second execution entities have user states defined by a program counter value, a context identifier value and N register values. To switch context, an execution entity such as a thread, while in user mode, writes the user state of the first execution entity to memory. It then restores the user state of the second execution entity by writing register values associated with the second execution entity to all but a first register and writing the context identifier value to a context identifier location.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: February 16, 1999
    Assignee: Silicon Graphics, Inc.
    Inventors: Nawaf K. Bitar, Robert M. English, Rajagopal Ananthanarayanan, Alexander D. Petruncola, David Craig