Abstract: Methods and apparatus including: setting up a plurality of configurations for a plurality of local oscillator (LO) paths of a carrier aggregation (CA) transceiver operating with a plurality of bands; calculating and comparing frequencies for each LO path of the plurality of LO paths and at least one divider ratio of LO dividers for each band of the plurality of bands to identify frequency conflicts; and reconfiguring the LO dividers for the plurality of LO paths and the plurality of bands when the frequency conflicts are identified.

Abstract: Multiplex modules for use in carrier aggregation receivers are disclosed. In an exemplary embodiment, an apparatus includes an LNA multiplexer configured to receive a plurality of RF signals at a plurality of input terminals and to combine the RF signals into a combined RF signal that is output from an output terminal The apparatus also includes an LNA demultiplexer configured to receive the combined RF signal at an input port that is connected to the output terminal and to distribute the combined RF signal to a plurality of output ports.

Abstract: An amplifier having a switchable common gate gain buffer is disclosed. In an exemplary embodiment, an apparatus includes a plurality of selectable gain channels that provide constant input impedance at a common input to receive an input signal and generate an output signal having at least one of selected gain and current characteristics. At least two gain channels utilize transistors having different transconductance values. The apparatus also includes at least one impedance network coupled to at least one gain channel to provide the constant input impedance.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for dynamically secondary cell (SCELL) allocation and frequency planning for carrier aggregation. One example system for radio frequency (RF) signal processing, generally includes a first integrated circuit (IC) comprising two or more receive chains, each receive chain for processing one of multiple component carriers in a carrier aggregation (CA) signal, wherein the first IC is configured to downconvert a signal associated with a primary cell of the CA signal; and a second IC configured to downconvert one or more signals associated with one or more secondary cells of the CA signal. The second IC may also be configured to upconvert a signal having a frequency different than the primary cell by an offset associated with the primary cell.

Abstract: A circuit, a method and an apparatus, are described. A radio frequency (RF) signal received from a transmission line is provided to the source of a transistor in a common-gate amplification circuit. A series resonance connected to the source provides a low impedance path to ground for interfering RF components in the RF signal. The series resonance is tuned to provide a high impedance to a band of frequencies centered on a frequency of interest and to shunt interfering RF components outside the band of frequencies centered on the frequency of interest. The interfering RF components may include a harmonic of the frequency of interest.

Abstract: A wideband frequency generator has two or more oscillators for different frequency bands, disposed on the same die within a flip chip package. Coupling between inductors of the two oscillators is reduced by placing one inductor on the die and the other inductor on the package, separating the inductors by a solder bump diameter. The loosely coupled inductors allow manipulation of the LC tank circuit of one of the oscillators to increase the bandwidth of the other oscillator, and vice versa. Preventing undesirable mode of oscillation in one of the oscillators may be achieved by loading the LC tank circuit of the other oscillator with a large capacitance, such as the entire capacitance of the coarse tuning bank of the other oscillator. Preventing the undesirable mode may also be achieved by decreasing the quality factor of the other oscillator's LC tank and thereby increasing the losses in the tank circuit.

Abstract: An amplifier having a switchable common gate gain buffer is disclosed. In an exemplary embodiment, an apparatus includes a plurality of selectable gain channels that provide constant input impedance at a common input to receive an input signal and generate an output signal having at least one of selected gain and current characteristics. At least two gain channels utilize transistors having different transconductance values. The apparatus also includes at least one impedance network coupled to at least one gain channel to provide the constant input impedance.

Abstract: Exemplary embodiments are directed to a programmable varactor device. A varactor device may include an input device configured to receive a tuning voltage and generate a bias voltage at least partially dependent on the tuning voltage. The varactor device may also include a varactor pair coupled to the input device and having a first variable capacitor and a second variable capacitor, wherein each of the first variable capacitor and a second variable capacitor are configured for operable coupling to each of the bias voltage and the tuning voltage.

Abstract: A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a phase and frequency detector. The frequency synthesizer circuit also includes a first charge pump and a second charge pump, each coupled to the phase and frequency detector. The frequency synthesizer circuit also includes a loop filter that includes a resistor and at least two capacitors. The second charge pump is coupled between the resistor and a capacitor that creates a zero in a transfer function of the loop filter. The frequency synthesizer circuit also includes a voltage controlled oscillator that produces an output frequency based on an output of the loop filter.

Abstract: A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a phase and frequency detector. The frequency synthesizer circuit also includes a first charge pump and a second charge pump, each coupled to the phase and frequency detector. The frequency synthesizer circuit also includes a loop filter that includes a resistor and at least two capacitors. The second charge pump is coupled between the resistor and a capacitor that creates a zero in a transfer function of the loop filter. The frequency synthesizer circuit also includes a voltage controlled oscillator that produces an output frequency based on an output of the loop filter.

Abstract: A method includes setting a mode of operation of a buffer circuit outputting an output signal. The mode of operation is set to a first mode of operation or a second mode of operation. The output signal is substantially in-phase with an input signal received by the buffer circuit when the mode of operation is the first mode. The output signal is substantially out of phase with the input signal when the mode of operation is the second mode.

Abstract: A circuit for a voltage controlled oscillator (VCO) buffer is described. The circuit includes a first capacitor connected to an input of the VCO buffer that is connected to a VCO core. The circuit also includes a second capacitor connected to the input of the VCO buffer and the gate of a p-type metal-oxide-semiconductor field effect (PMOS) transistor. The circuit further includes a first switch connected to the first capacitor and the gate of the PMOS transistor. The circuit also includes a third capacitor connected to the input of the VCO buffer. The circuit further includes a fourth capacitor connected to the input of the VCO buffer and the gate of an n-type metal-oxide-semiconductor field effect (NMOS) transistor. The circuit also includes a second switch connected to the third capacitor and the gate of the NMOS transistor.

Abstract: Disclosed are circuits, techniques and methods for buffering a high frequency signal for transmission over an integrated circuit. In one particular implementation, a plurality of amplification circuits are individually biased for amplifying a signal from a voltage controlled oscillator and/or digitally controlled oscillator to provide a local oscillator signal on a device.

Abstract: A method includes setting a mode of operation of a buffer circuit outputting an output signal. The mode of operation is set to a first mode of operation or a second mode of operation. The output signal is substantially in-phase with an input signal received by the buffer circuit when the mode of operation is the first mode. The output signal is substantially out of phase with the input signal when the mode of operation is the second mode.

Abstract: A wideband frequency generator has two or more oscillators for different frequency bands, disposed on the same die within a flip chip package. Coupling between inductors of the two oscillators is reduced by placing one inductor on the die and the other inductor on the package, separating the inductors by a solder bump diameter. The loosely coupled inductors allow manipulation of the LC tank circuit of one of the oscillators to increase the bandwidth of the other oscillator, and vice versa. Preventing undesirable mode of oscillation in one of the oscillators may be achieved by loading the LC tank circuit of the other oscillator with a large capacitance, such as the entire capacitance of the coarse tuning bank of the other oscillator. Preventing the undesirable mode may also be achieved by decreasing the quality factor of the other oscillator's LC tank and thereby increasing the losses in the tank circuit.

Abstract: A wideband frequency generator has two or more oscillators for different frequency bands, disposed on the same die within a flip chip package. Coupling between inductors of the two oscillators is reduced by placing one inductor on the die and the other inductor on the package, separating the inductors by a solder bump diameter. The loosely coupled inductors allow manipulation of the LC tank circuit of one of the oscillators to increase the bandwidth of the other oscillator, and vice versa. Preventing undesirable mode of oscillation in one of the oscillators may be achieved by loading the LC tank circuit of the other oscillator with a large capacitance, such as the entire capacitance of the coarse tuning bank of the other oscillator. Preventing the undesirable mode may also be achieved by decreasing the quality factor of the other oscillator's LC tank and thereby increasing the losses in the tank circuit.

Abstract: A capacitance switching element includes first and second capacitors connected in series by transistors. The gates of the transistors are biased by a first signal through one set of resistors, and the sources and drains are biased by a second signal through a second set of resistors. The signals are level-shifted and may be complimentary. To turn the element ON, the first signal may be set to VDD and the second signal may be set to zero. To turn the element OFF, the first signal may be set to a multiple of VDD/2 and the second signal may be set to the multiple plus one of VDD/2. When the element is used in an oscillator tuning circuit, the voltage stress on the transistors is reduced and the transistors may be fabricated with thin oxide. The oscillator may be used in a transceiver of a cellular access terminal.

Abstract: An oscillator includes a resonator, a first and a second p-type transistor, and a first and a second n-type transistor. The resonator has a first terminal and a second terminal. The first p-type transistor is switchably connected to the first terminal while the second p-type transistor is switchably connected to the second terminal. A first drain of the first n-type transistor and the second drain of the second n-type transistor are electrically connected to the first terminal and the second terminal, respectively. The oscillator is capable of operating in an NMOS only mode and in a CMOS mode.

Abstract: An RF buffer circuit for a voltage controlled oscillator (VCO) includes dynamic biasing circuitry to selectively flip the phase of the output voltage waveform. In a CMOS implementation, a PMOS/NMOS pair is employed in an output path. During a high (voltage) swing mode condition, the phase of the output is flipped such that the output waveform is in phase with the voltages appearing at the gates of the PMOS/NMOS pair. The technique thereby reduces peak gate-to-drain voltages and allows for improved reliability of the MOS devices in a configuration amenable to low phase noise and low power consumption.

Abstract: Disclosed are circuits, techniques and methods for buffering a high frequency signal for transmission over an integrated circuit. In one particular implementation, a plurality of amplification circuits are individually biased for amplifying a signal from a voltage controlled oscillator and/or digitally controlled oscillator to provide a local oscillator signal on a device.