Patents by Inventor Rajamani Sethuram

Rajamani Sethuram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
    Patent number: 9584120
    Abstract: Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: February 28, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Rajamani Sethuram, Karim Arabi
  • Method and apparatus for characterizing thermal marginality in an integrated circuit
    Patent number: 9285418
    Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Tapan J Chakraborty, Rajamani Sethuram, Ratibor Radojcic
  • METHOD AND APPARATUS FOR CHARACTERIZING THERMAL MARGINALITY IN AN INTEGRATED CIRCUIT
    Publication number: 20130285687
    Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.
    Type: Application
    Filed: March 11, 2013
    Publication date: October 31, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Tapan J. Chakraborty, Rajamani Sethuram, Riko Radojcic
  • INTEGRATED CIRCUIT LEAKAGE POWER REDUCTION USING ENHANCED GATED-Q SCAN TECHNIQUES
    Publication number: 20130241593
    Abstract: Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
    Type: Application
    Filed: May 6, 2013
    Publication date: September 19, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Rajamani Sethuram, Karim Arabi
  • Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
    Patent number: 8456193
    Abstract: Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: June 4, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Rajamani Sethuram, Karim Arabi
  • TESTING STACKED DIE
    Publication number: 20130043897
    Abstract: An integrated circuit configured for at-speed testing is described. The integrated circuit includes a first die. The first die includes a transition launch point. The integrated circuit also includes a second die. The second die includes a first observe point. The integrated circuit further includes a first through silicon via. The first through silicon via couples the first die to the second die.
    Type: Application
    Filed: January 30, 2012
    Publication date: February 21, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Rajamani Sethuram, Karim Arabi, Sarath Chandra Kasarla
  • Integrated Circuit Leakage Power Reduction using Enhanced Gated-Q Scan Techniques
    Publication number: 20120068734
    Abstract: Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Rajamani Sethuram, Karim Arabi