Abstract: An improved flip chip assembly is disclosed of the type where a semiconductor chip having a certain thermal expansion coefficient is directly mounted via solder bumps on the metallization pattern of a circuit substrate having a different thermal expansion coefficient. A base layer comprised of a polymer material is disposed over the surface of the chip, between the chip and the substrate, and the solder bumps are placed over the base layer; the base layer modifies the effective thermal expansion coefficient of the solder bumps to approximate that of the substrate, thus reducing the thermal expansion coefficient differential at the junction of the chip and the substrate.

Abstract: A grating fabrication process utilizes real-time measurement of a grating characteristic (such as, for example, grating period chirp, reflectivity, group delay) as a feedback error signal to modify the writing process and improve the characteristics of the finished grating. A test beam is launched through the optical medium during the writing process (or at the end of an initial writing process) and a particular characteristic is measured and used to generate a “corrective” apodization refractive index profile that can be incorporated with the grating to improve its characteristics. The improvements may be applied to a phase (or amplitude) mask used to write the grating (etching, local deformation, coating changes, for example), or the grating itself may be corrected using additional UV exposure, non-uniform annealing, non-uniform heating, and/or non-uniform tension—these techniques applied separately or in an intermittent sequence.

Abstract: A grating fabrication process utilizes real-time measurement of a grating characteristic (such as, for example, grating period chirp, reflectivity, group delay) as a feedback error signal to modify the writing process and improve the characteristics of the finished grating. A test beam is launched through the optical medium during the writing process (or at the end of an initial writing process) and a particular characteristic is measured and used to generate a “corrective” apodization refractive index profile that can be incorporated with the grating to improve its characteristics. The improvements may be applied to a phase (or amplitude) mask used to write the grating (etching, local deformation, coating changes, for example), or the grating itself may be corrected using additional UV exposure, non-uniform annealing, non-uniform heating, and/or non-uniform tension—these techniques applied separately or in an intermittent sequence.

Abstract: An improved flip chip assembly is disclosed of the type where a semiconductor chip having a certain thermal expansion coefficient is directly mounted via solder bumps on the metallization pattern of a circuit substrate having a different thermal expansion coefficient. A base layer comprised of a polymer material is disposed over the surface of the chip, between the chip and the substrate, and the solder bumps are placed over the base layer; the base layer modifies the effective thermal expansion coefficient of the solder bumps to approximate that of the substrate, thus reducing the thermal expansion coefficient differential at the junction of the chip and the substrate.

Abstract: An improved flip chip assembly is disclosed of the type where a semiconductor chip having a certain thermal expansion coefficient is directly mounted via solder bumps on the metallization pattern of a circuit substrate having a different thermal expansion coefficient. A base layer comprised of a polymer material is disposed over the surface of the chip, between the chip and the substrate, and the solder bumps are placed over the base layer; the base layer modifies the effective thermal expansion coefficient of the solder bumps to approximate that of the substrate, thus reducing the thermal expansion coefficient differential at the junction of the chip and the substrate.

Abstract: A semiconductor chip (10) has a plurality of metallized members (12) that are each advantageously bumped with a volume of gallium amalgam (18) to render the members wettable by a conventional solder.

Abstract: A solder self-alignment process for aligning a semiconductor chip (13) with, and bonding the chip to, a substrate (12) is preformed in an atmosphere rich in gaseous formic acid, at least during the melting step. It is preferred that the formic acid atmosphere be maintained during the self-alignment step and the step of cooling and hardening the solder elements (23). With this feature, one can completely avoid the use of any solid or liquid fluxes and avoid the consequences of such use. Nonetheless, the molten solder elements (23) dependably bond to the bonding surfaces and vertically align themselves.