Patents by Inventor Rajan K. Pandey

Rajan K. Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230299170
    Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
    Type: Application
    Filed: August 31, 2022
    Publication date: September 21, 2023
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 10366897
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 10347494
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 10319596
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 10170576
    Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20180226257
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 9, 2018
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 9984883
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 9972497
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20180096851
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Application
    Filed: November 16, 2017
    Publication date: April 5, 2018
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20180083116
    Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 22, 2018
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20170278713
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 9735250
    Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 9705079
    Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
  • Patent number: 9680096
    Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
  • Publication number: 20170148890
    Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
    Type: Application
    Filed: July 28, 2016
    Publication date: May 25, 2017
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20170148892
    Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 25, 2017
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 9647210
    Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
  • Patent number: 9627484
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20170104066
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Application
    Filed: October 12, 2015
    Publication date: April 13, 2017
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20170103897
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Application
    Filed: August 2, 2016
    Publication date: April 13, 2017
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan