Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.

Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.

Abstract: A base transceiver station (BTS) includes dedicated memories to store uplink real-time (RT) data received by way of an antenna of the BTS and downlink RT data generated by processors of the BTS. The dedicated memories serve a dedicated number of processors, which prevents over-run and under-run of antenna buffers and provides deterministic data flow necessary to stream time-critical uplink and downlink RT data. Thus, a high and dedicated bandwidth for the uplink and downlink RT data is ensured.

Abstract: A base transceiver station (BTS) includes dedicated memories to store uplink real-time (RT) data received by way of an antenna of the BTS and downlink RT data generated by processors of the BTS. The dedicated memories serve a dedicated number of processors, which prevents over-run and under-run of antenna buffers and provides deterministic data flow necessary to stream time-critical uplink and downlink RT data. Thus, a high and dedicated bandwidth for the uplink and downlink RT data is ensured.

Abstract: A system for merging first and second interrupts includes first and second queue modules, first and second status modules, and first and second merger modules. The first and second queue modules receive first and second en-queue signals corresponding to the first and second interrupts, first and second de-queue signals, and generate first and second status signals. The first and second status modules receive first and second status signals, and first and second output signals, and generate first and second merge signals. The first and second merger modules receive the first and second merge signals, and generate the first and second output signals. One of the first and second output signals is indicative of the first and second en-queue signals, thereby merging the first and second interrupts into at least one of the first and second output signals.

Abstract: A system for merging first and second interrupts includes first and second queue modules, first and second status modules, and first and second merger modules. The first and second queue modules receive first and second en-queue signals corresponding to the first and second interrupts, first and second de-queue signals, and generate first and second status signals. The first and second status modules receive first and second status signals, and first and second output signals, and generate first and second merge signals. The first and second merger modules receive the first and second merge signals, and generate the first and second output signals. One of the first and second output signals is indicative of the first and second en-queue signals, thereby merging the first and second interrupts into at least one of the first and second output signals.

Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a transmission configuration. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in various transmission configurations.

Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a transmission configuration. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in various transmission configurations.

Abstract: A system for transferring data between asynchronous domains in an SOC includes a slave request generation and data latch circuit, a busy signal generator, a positive edge detector, and a cascaded synchronizer. A host device transmits a host request signal and host data to the slave request generation and data latch circuit for execution by a slave device, which operates at a different frequency than the host device. The slave request generation and data latch circuit stores the host data and transmits it to the slave device based on a synchronized slave clock signal. The host device can perform other tasks while the slave device executes the host request.

Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a cellular network. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in multiple cellular networks.

Abstract: A system for transferring data between asynchronous domains in an SOC includes a slave request generation and data latch circuit, a busy signal generator, a positive edge detector, and a cascaded synchronizer. A host device transmits a host request signal and host data to the slave request generation and data latch circuit for execution by a slave device, which operates at a different frequency than the host device. The slave request generation and data latch circuit stores the host data and transmits it to the slave device based on a synchronized slave clock signal. The host device can perform other tasks while the slave device executes the host request.

Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a cellular network. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in multiple cellular networks.

Abstract: A method for detecting a type of a port connected to a USB connector and a rechargeable device with a USB connector, a USB controller and a power management module. The power management module selectively powers up the USB controller depending on the type of port connected to the USB connector. A hardware detector is connected to the USB connector for determining the port type. If the port type is for recharging only then the power management module does not enable power to the USB controller.

Abstract: A method and system for managing communications between sub-systems of a communication device. The sub-systems include a Radio Frequency Integrated Circuit (RFIC) and a Baseband Integrated Circuit (BBIC). The BBIC includes a processing engine, a state machine module and an interface module. The method includes initializing a Digital Radio Frequency Third Generation (DigRF3G) interface between the RFIC and the BBIC. The processing engine is kept functionally inactive during the initialization process of the DigRF3G interface. Further, the method includes exchanging one or more packets between the RFIC and the BBIC.

Abstract: A method for detecting a type of a port connected to a USB connector and a rechargeable device with a USB connector, a USB controller and a power management module. The power management module selectively powers up the USB controller depending on the type of port connected to the USB connector. A hardware detector is connected to the USB connector for determining the port type. If the port type is for recharging only then the power management module does not enable power to the USB controller.

Abstract: A method and system for managing communications between sub-systems of a communication device. The sub-systems include a Radio Frequency Integrated Circuit (RFIC) and a Baseband Integrated Circuit (BBIC). The BBIC includes a processing engine, a state machine module and an interface module. The method includes initializing a Digital Radio Frequency Third Generation (DigRF3G) interface between the RFIC and the BBIC. The processing engine is kept functionally inactive during the initialization process of the DigRF3G interface. Further, the method includes exchanging one or more packets between the RFIC and the BBIC.