Abstract: A tPEN layer (108) having a tensile stress is formed over a conductive gate stack (104-106) provided on a semiconductor substrate. Following the formation of the conductive gate stack (104-106), an anneal is performed. The conductive gate stack includes a metal layer to prevent outgassing and poly depletion during the anneal. Next, a photoresist layer (110) is formed and patterned to form a gate (122, 124).

Abstract: A process for forming a silicided MOS transistor (100) begins by providing source and drain regions (104) and (106) and a gate electrode (110). Silicon nitride spacers (116) are formed adjacent the gate electrode (110). A cobalt layer (118) and an overlying titanium layer (120) are then deposited in contact with the regions (104), (106), and (110). A rapid thermal process (130) is then used to react the titanium, cobalt, and silicon together to form silicide regions (124), (126), and (128), and intermetallic compound layers (132) and (134). The intermetallic compound layers (132) and (134) are then etched using two sequentially-performed wet etch steps (136) and (138). The resulting structure (100) has a nitride spacer (116) and field oxide regions (107) which are free from cobalt residual contamination (38).

Abstract: Vibrating and oscillating rates can be dynamically changed during polishing to achieve an optimal polishing process. A semiconductor device substrate (34) has a first layer with a first film (12) and a second film (10) that overlies the first film (12), where the first film (12) is harder and underlies the second film (10). In one embodiment, the substrate (34) is placed over a first region (66) of a polishing pad (60). The second film (10) is polished at a first vibrating and oscillating rates over the first region (66). An endpoint signal is received when the first film (12) is reached. The substrate (34) is moved to a second region (62) of the polishing pad (60) that is closer to the edge of the pad and has a higher feature density compared to the first region (66). Polishing is performed at a second vibrating and oscillating rates that are different from the first vibrating and oscillating rates to remove the first film (10).

Abstract: Vibrating and oscillating rates can be dynamically changed during polishing to achieve an optimal polishing process. A semiconductor device substrate (34) has a first layer with a first film (12) and a second film (10) that overlies the first film (12), where the first film (12) is harder and underlies the second film (10). In one embodiment, the substrate (34) is placed over a first region (66) of a polishing pad (60). The second film (10) is polished at a first vibrating and oscillating rates over the first region (66). An endpoint signal is received when the first film (12) is reached. The substrate (34) is moved to a second region (62) of the polishing pad (60) that is closer to the edge of the pad and has a higher feature density compared to the first region (66). Polishing is performed at a second vibrating and oscillating rates that are different from the first vibrating and oscillating rates to remove the first film (10).

Abstract: A method for forming a contact structure (10) which enables the use of ultra-shallow source/drain junctions begins by forming source and drain regions (14) and gate electrode (16). The source and drain regions (14) and the gate electrode (16) are silicided to form silicide regions (20). A conductive tungsten nitride etch stop layer (22) is formed overlying the silicide regions (20). Contact plug regions (28) are then formed to contact to the etch stop layer (22) and silicided regions (20). At this point, all of the silicide regions (20) are electrically short circuited. To remove this electric short circuit, an isotropic etch process comprising hydrogen peroxide, ammonium hydroxide, and water is used to remove portions of the tungsten nitride regions which are between the individual contact portions (28) in a self-aligned manner.

Abstract: A semiconductor device (10) includes a gate electrode (61) having a silicon/tungsten nitride/tungsten silicon nitride/tungsten silicide composition. The tungsten nitride film (21) and tungsten suicide film (23) are formed using chemical vapor deposition (CVD). The tungsten nitride film is formed using a tungsten halide and N.sub.2 R.sup.1 R.sup.2, where each of R.sup.1 and R.sup.2 is hydrogen, an alkyl group, an alkenyl group, or an alkynyl group. The tungsten nitride film (21) is an etch stop when patterning the tungsten silicide film (23). The CVD tungsten nitride film (21) helps to improve gate dielectric integrity and reduces interface traps when compared to a sputtered tungsten nitride film (21). Also, N.sub.2 R.sup.1 R.sup.2 can be used to remove halogens that are adsorbed onto walls of a reaction chamber than is cleaned between depositions of substrates.