Patents by Inventor Rajan Raghvendra

Rajan Raghvendra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ADAPTIVE CLOCK SIGNAL FREQUENCY SCALING
    Publication number: 20240143060
    Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: MAXLINEAR, INC.
    Inventors: Chunfeng Hu, Rajan Raghvendra
  • Adaptive clock signal frequency scaling
    Patent number: 11868194
    Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: January 9, 2024
    Assignee: MaxLinear, Inc.
    Inventors: Chunfeng Hu, Rajan Raghvendra
  • ADAPTIVE CLOCK SIGNAL FREQUENCY SCALING
    Publication number: 20220391000
    Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 8, 2022
    Inventors: Chunfeng Hu, Rajan Raghvendra
  • Adaptive clock signal frequency scaling
    Patent number: 11360539
    Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 14, 2022
    Assignee: MaxLinear, Inc.
    Inventors: Chunfeng Hu, Rajan Raghvendra
  • ADAPTIVE CLOCK SIGNAL FREQUENCY SCALING
    Publication number: 20190041945
    Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.
    Type: Application
    Filed: September 18, 2018
    Publication date: February 7, 2019
    Inventors: Chunfeng Hu, Rajan Raghvendra