Patents by Inventor Rajan V. K. Pillai

Rajan V. K. Pillai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7089481
    Abstract: Techniques for performing substantially concurrent add-compare-select-add operations and substantially concurrent compare-select-add operations for use in turbo decoders are provided. In one aspect of the invention, a technique for processing data in accordance with a turbo decoder comprises the following steps. Data values of two sets of input data are respectively added to generate a set of sums. Substantially concurrent with the addition step, correction values are respectively added to the sums to generate a set of corrected sums. Substantially concurrent with the respective input data value and correction value addition steps, the sums are compared against one another, and an absolute value of a difference between the sums is compared against base and bound values. Then, one of the corrected sums is selected based on the comparison steps. Preferably, respective sub-steps within the input value addition step, the correction value addition step, and the comparison step are performed concurrently.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: August 8, 2006
    Assignee: Agere Systems Inc.
    Inventors: Paul Gerard D'Arcy, Rajan V. K. Pillai
  • Patent number: 7020830
    Abstract: Techniques are provided for the addition and comparison operations associated with a Viterbi decoding algorithm at substantially the same time. To this end, an operation of the type a±b>c±d (where a and b are to be added, c and d are to be added, and then the sums compared to determine the larger of the two sums) can be formulated, in accordance with the invention, into a±b?c?d>0 (where the addition of a and b and of c and d, and their comparison, are substantially concurrently performed). More specifically, in order to facilitate substantially concurrent addition and comparison operations in a Viterbi decoder, in one embodiment, the present invention performs multi-operand addition in a carry save form. With the results of addition represented in carry save form, the evaluation of comparator conditions is relatively straightforward.
    Type: Grant
    Filed: December 24, 2001
    Date of Patent: March 28, 2006
    Assignee: Agere Systems Inc.
    Inventors: Paul Gerard D'Arcy, Rajan V. K. Pillai
  • Publication number: 20040015773
    Abstract: Techniques for performing substantially concurrent add-compare-select-add operations and substantially concurrent compare-select-add operations for use in turbo decoders are provided. In one aspect of the invention, a technique for processing data in accordance with a turbo decoder comprises the following steps. Data values of two sets of input data are respectively added to generate a set of sums. Substantially concurrent with the addition step, correction values are respectively added to the sums to generate a set of corrected sums. Substantially concurrent with the respective input data value and correction value addition steps, the sums are compared against one another, and an absolute value of a difference between the sums is compared against base and bound values. Then, one of the corrected sums is selected based on the comparison steps. Preferably, respective sub-steps within the input value addition step, the correction value addition step, and the comparison step are performed concurrently.
    Type: Application
    Filed: July 22, 2002
    Publication date: January 22, 2004
    Inventors: Paul Gerard D'Arcy, Rajan V.K. Pillai
  • Publication number: 20030120996
    Abstract: Techniques are provided for the addition and comparison operations associated with a Viterbi decoding algorithm at substantially the same time. To this end, an operation of the type a±b>c±d (where a and b are to be added, c and d are to be added, and then the sums compared to determine the larger of the two sums) can be formulated, in accordance with the invention, into a±b−c∓d>0 (where the addition of a and b and of c and d, and their comparison, are substantially concurrently performed). More specifically, in order to facilitate substantially concurrent addition and comparison operations in a Viterbi decoder, in one embodiment, the present invention performs multi-operand addition in a carry save form. With the results of addition represented in carry save form, the evaluation of comparator conditions is relatively straightforward.
    Type: Application
    Filed: December 24, 2001
    Publication date: June 26, 2003
    Inventors: Paul Gerard D'Arcy, Rajan V.K. Pillai