Abstract: Methods and wafers for vertical gradient freeze 8 inch gallium arsenide (GaAs) substrates. In disclosed examples, vertical gradient freeze systems for forming gallium arsenide (GaAs) substrates having silicon as a dopant, the system includes a crucible to contain a GaAs liquid melt and seed material during a formation process; one or more heating coils arranged in a plurality of heating zones; and a pedestal to move relative to the crucible, the system operable to control heating of the plurality of heating zones and movement of the pedestal to form a single crystal GaAs substrate.

Abstract: Methods and systems for low etch pit density gallium arsenide crystals with boron dopant may include a gallium arsenide single crystal wafer having boron as a dopant, an etch pit density of less than 500 cm?2, and optical absorption of 6 cm?1 or less at 940 nm. The wafer may have an etch pit density of less than 200 cm?2. The wafer may have a diameter of 6 inches or greater. The wafer may have a boron concentration between 1×1019 cm?3 and 2×1019 cm?3. The wafer may have a thickness of 300 ?m or greater. Optoelectronic devices may be formed on a first surface of the wafer, which may be diced into a plurality of die and optical signals from an optoelectronic device on one side of one of the die may be communicated out a second side of the die opposite to the one side.

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.

Abstract: Methods and wafers for vertical gradient freeze 8 inch gallium arsenide (GaAs) substrates. In disclosed examples, vertical gradient freeze systems for forming gallium arsenide (GaAs) substrates having silicon as a dopant, the system includes a crucible to contain a GaAs liquid melt and seed material during a formation process; one or more heating coils arranged in a plurality of heating zones; and a pedestal to move relative to the crucible, the system operable to control heating of the plurality of heating zones and movement of the pedestal to form a single crystal GaAs substrate.

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.

Abstract: Methods and wafers for vertical gradient freeze 8 inch gallium arsenide (GaAs) substrates. In disclosed examples, vertical gradient freeze systems for forming gallium arsenide (GaAs) substrates having silicon as a dopant, the system includes a crucible to contain a GaAs liquid melt and seed material during a formation process; one or more heating coils arranged in a plurality of heating zones; and a pedestal to move relative to the crucible, the system operable to control heating of the plurality of heating zones and movement of the pedestal to form a single crystal GaAs substrate.

Abstract: A germanium single-crystal wafer comprises silicon with an atomic concentration of from 3×1014 atoms/cc to 10×1013 atoms/cc, boron with an atomic concentration of from 1×1016 atoms/cc to 10×1018 atoms/cc, and gallium with an atomic concentration of from 1×1016 atoms/cc to 10×1019 atoms/cc. Further provided are a method for preparing the germanium single-crystal wafer, a method for preparing a germanium single-crystal ingot, and the use of the germanium single-crystal wafer for increasing the open-circuit voltage of a solar cell. The germanium single-crystal wafer has an improved electrical property in that it has a smaller difference in resistivity and carrier concentration.

Abstract: A monocrystalline germanium wafer that increases the open-circuit voltage of multijunction solar cells, a method for preparing the monocrystalline germanium wafer and a method for preparing an ingot from which the monocrystalline germanium wafer is prepared. The monocrystalline germanium wafer that increases the open-circuit voltage of the bottom cell of multijunction solar cells is prepared by adjusting the amounts of the co-dopants silicon and gallium in the monocrystalline germanium wafer, the ratio of silicon to gallium in the preparation of the monocrystalline germanium.

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.

Abstract: Methods and systems for low etch pit density gallium arsenide crystals with boron dopant may include a gallium arsenide single crystal wafer having boron as a dopant, an etch pit density of less than 500 cm?2, and optical absorption of 6 cm?1 or less at 940 nm. The wafer may have an etch pit density of less than 200 cm?2. The wafer may have a diameter of 6 inches or greater. The wafer may have a boron concentration between 1×1019 cm?3 and 2×1019 cm?3. The wafer may have a thickness of 300 ?m or greater. Optoelectronic devices may be formed on a first surface of the wafer, which may be diced into a plurality of die and optical signals from an optoelectronic device on one side of one of the die may be communicated out a second side of the die opposite to the one side.