Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to column readout circuitry. A given image pixel may generate a low light signal and a high light signal for a given exposure. A column line may couple the given image pixel to readout circuitry having amplifier circuitry. The column line may be coupled to an autozeroing transistor for reading out the high light signal and a source follower stage for readout out the low light signal. The amplifier circuitry may receive different common mode voltage depending on whether it is amplifying the low or high light signal. The gain and other operating parameters of the amplifier circuitry may be adjusted based on whether it is amplifying the low or high signal. If desired, separate amplifier circuitry may be implemented for the low and high light signals.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to column readout circuitry. A given image pixel may generate a low light signal and a high light signal for a given exposure. A column line may couple the given image pixel to readout circuitry having amplifier circuitry. The column line may be coupled to an autozeroing transistor for reading out the high light signal and a source follower stage for readout out the low light signal. The amplifier circuitry may receive different common mode voltage depending on whether it is amplifying the low or high light signal. The gain and other operating parameters of the amplifier circuitry may be adjusted based on whether it is amplifying the low or high signal. If desired, separate amplifier circuitry may be implemented for the low and high light signals.

Abstract: An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to column readout circuitry via a corresponding column line. The column readout circuitry may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry may include split MSB and LSB capacitor banks. The MSB capacitor bank may include capacitors selectively coupled to a coarse reference voltage or a fine reference voltage. The LSB capacitor bank may include capacitors electively coupled to the coarse reference voltage.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to column readout circuitry. A given image pixel may generate a low light signal and a high light signal for a given exposure. A column line may couple the given image pixel to readout circuitry having amplifier circuitry. The column line may be coupled to an autozeroing transistor for reading out the high light signal and a source follower stage for readout out the low light signal. The amplifier circuitry may receive different common mode voltage depending on whether it is amplifying the low or high light signal. The gain and other operating parameters of the amplifier circuitry may be adjusted based on whether it is amplifying the low or high signal. If desired, separate amplifier circuitry may be implemented for the low and high light signals.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.

Abstract: An image sensor may include an array of image pixels. The image pixel pixels may be arranged in columns and rows. Each column of image pixels may be coupled to column readout circuitry via respective column lines. The column readout circuitry may include amplifier circuitry, a first source follower stage, and a second source follower stage. The first and second source follower stages may be interposed between the amplifier circuitry and a sampling capacitor. A switch may be interposed between the first and second source follower stages. The second source follower transistor may be configured to provide an intermediate sampling voltage to the sampling capacitor. The first source follower transistor may be configured to provide a final sampling voltage to the sampling capacitor. In such a manner, kickback from sampling signals using readout circuitry may be reduced.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to column readout circuitry. A given image pixel may generate a low light signal and a high light signal for a given exposure. A column line may couple the given image pixel to readout circuitry having amplifier circuitry. The column line may be coupled to an autozeroing transistor for reading out the high light signal and a source follower stage for readout out the low light signal. The amplifier circuitry may receive different common mode voltage depending on whether it is amplifying the low or high light signal. The gain and other operating parameters of the amplifier circuitry may be adjusted based on whether it is amplifying the low or high signal. If desired, separate amplifier circuitry may be implemented for the low and high light signals.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.

Abstract: An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to column readout circuitry via a corresponding column line. The column readout circuitry may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry may include split MSB and LSB capacitor banks. The MSB capacitor bank may include capacitors selectively coupled to a coarse reference voltage or a fine reference voltage. The LSB capacitor bank may include capacitors electively coupled to the coarse reference voltage.

Abstract: An image sensor may include an array of image pixels. The image pixel pixels may be arranged in columns and rows. Each column of image pixels may be coupled to column readout circuitry via respective column lines. The column readout circuitry may include amplifier circuitry, a first source follower stage, and a second source follower stage. The first and second source follower stages may be interposed between the amplifier circuitry and a sampling capacitor. A switch may be interposed between the first and second source follower stages. The second source follower transistor may be configured to provide an intermediate sampling voltage to the sampling capacitor. The first source follower transistor may be configured to provide a final sampling voltage to the sampling capacitor. In such a manner, kickback from sampling signals using readout circuitry may be reduced.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.