Patents by Inventor Rajashekar Reddy

Rajashekar Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12190113
    Abstract: A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: January 7, 2025
    Assignee: Deep Vision Inc.
    Inventors: Mohamed Shahim, Raju Datla, Abhilash Bharath Ghanore, Lava Kumar Bokam, Suresh Kumar Vennam, Rajashekar Reddy Ereddy
  • Publication number: 20240409115
    Abstract: This document describes techniques and systems for autonomous parking in locations without cellular coverage. A system can include a processor that obtains a request to autonomously park in a parking environment. The system can then determine whether parking space information indicating an available space was obtained. In response to determining that parking space information was obtained, the system can autonomously operate the host vehicle to navigate to and park in the available space. The system determines whether a communication system of the host vehicle has a cellular connection available to aid in the navigation. In response to a determination that the cellular connection is not available, the system communicates the location of the host vehicle to the processor via a proxy vehicle with an operable cellular connection. By utilizing a mesh network among vehicles to share their cellular connections, autonomous parking features may remain available in locations without cellular coverage.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Inventors: Rajashekar Reddy Billapati, Kanishka Tyagi, Sruthi Kilari
  • Publication number: 20240403668
    Abstract: Application prototyping systems and methods are disclosed. One aspect is a processing method for multiple computing devices that includes identifying resource constraints for the multiple computing devices. Using identified resource constraints, multiple presentation models at least in part based on identified processing metrics are created. In one aspect, the multiple presentation models include multiple processing pipelines configurable for execution on multiple computing devices. An inference engine can be used to provide an execution model for the multiple processing pipelines based at least in part on the multiple presentation models, with the execution model having improved processing metrics as compared to at least one of the multiple presentation models.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Abhilash Bharath Ghanore, Suresh Lakshmi Goduguluru, Rajashekar Reddy Ereddy, Sreenivas Aerra Reddy, Satya Uppalapati, Lava Kumar Bokam, Siva Kumar Vemuri, Arindam Chakraborty, Snigdha Alkanti, Divyansh Agrawal, Amit Pandey
  • Publication number: 20240403667
    Abstract: Application prototyping systems and methods are disclosed. One aspect is a processing method for multiple computing devices that includes identifying resource constraints for the multiple computing devices. Using identified resource constraints, a presentation model having a plurality of modifiable parameters based at least in part based on the resource constraints is created. At least one inference engine supporting neural network processing is used to execute a particular neural network model based at least in part on the presentation model.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Abhilash Bharath Ghanore, Suresh Lakshmi Goduguluru, Rajashekar Reddy Ereddy, Sreenivas Aerra Reddy, Satya Uppalapati, Lava Kumar Bokam, Siva Kumar Vemuri, Arindam Chakraborty, Snigdha Alkanti, Davyansh Agrawal, Amit Pandey
  • Publication number: 20240192200
    Abstract: The invention relates to a portable device for testing agro-dairy based samples. The said device comprises an optical detector based on micro-spectroscopy. With the aid of an adaptor, the device is amenable to holding a colorimetric test strip, a concave shaped holder for a solid or semi-solid substance and/or a cuvette. The invention also describes a system of testing agro-dairy based samples comprising the said portable device and also a method of testing agro-dairy based samples using the said system.
    Type: Application
    Filed: May 6, 2022
    Publication date: June 13, 2024
    Applicant: Faunatech Solutions Private Limited
    Inventors: Rajat Pandya, Sidhant Jena, Sandhyaa Subramanian, Rajashekar Reddy Palvalli
  • Publication number: 20230409936
    Abstract: Proxy systems and methods for multiprocessing architectures are described. One method includes receiving an inference request and a statistics request from a client computing system. The method may access a load state of each processing device in a subset of processing devices preloaded with the neural network model, and select a target processing device from the subset based on the load states. One aspect includes transmitting the inference request to the target processing device, and monitoring an execution of the inference request by the target processing device based on the neural network model. The method may receive an inference result generated by the target processing device after executing the inference request, and compute an average inference time for the inference request execution based on the monitoring. The method may transmit the inference result and the average inference time to the client computing system.
    Type: Application
    Filed: May 17, 2023
    Publication date: December 21, 2023
    Inventors: Lava Kumar Bokam, Sriduth Jayhari, Divya Vipin, Rajashekar Reddy Ereddy, Snigdha Alkanti, Venkateswara Rao Andole Mankali, Suresh Kumar Vennam, Mohammed Mujahid, Sreenivas Aerra Reddy
  • Publication number: 20230376728
    Abstract: Proxy systems and methods for multiprocessing architectures are described. One method includes receiving a neural network model from a client computing system. System resource availability on a plurality of processing devices may be assessed, and a subset of available processing devices may be selected based on the system resource availability. In one aspect, the neural network model is loaded into each processing device in the subset. The method may include receiving an inference request from the client computing system. A load state of each processing device in the subset may be accessed, and a target processing device from the subset may be selected based on the load states. The inference request may be transmitted to the target processing device.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 23, 2023
    Inventors: Lava Kumar Bokam, Sriduth Jayhari, Divya Vipin, Rajashekar Reddy Ereddy, Snigdha Alkanti, Venkateswara Rao Andole Mankali, Suresh Kumar Vennam, Mohammed Mujahid, Sreenivas Aerra Reddy
  • Publication number: 20230315464
    Abstract: A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Inventors: Mohamed Shahim, Raju Datla, Abhilash Bharath Ghanore, Lava Kumar Bokam, Suresh Kumar Vennam, Rajashekar Reddy Ereddy
  • Patent number: 11714651
    Abstract: A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: August 1, 2023
    Assignee: Deep Vision Inc.
    Inventors: Mohamed Shahim, Raju Datla, Abhilash Bharath Ghanore, Lava Kumar Bokam, Suresh Kumar Vennam, Rajashekar Reddy Ereddy
  • Patent number: 11341246
    Abstract: An information handling system may include a host system comprising a host system processor, a management controller coupled to the host system processor, and an information handling resource coupled to the host system processor and the management controller, the information handling resource including a firmware. The information handling system may be configured to transfer a firmware update package from the host system to the management controller, wherein the firmware update package includes a cryptographic signature; verify, at the management controller, the cryptographic signature; transfer data indicative of the verification from the management controller to the information handling resource; and in response to receiving the data indicative of the verification from the management controller, install, by the information handling resource, the firmware update package.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 24, 2022
    Assignee: Dell Products L.P.
    Inventors: Santosh Gore, Raveendra Babu Madala, Viswanath Ponnuru, Deepu Syam Sreedhar M, Sura Rajashekar Reddy
  • Publication number: 20210373792
    Abstract: A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 2, 2021
    Inventors: Mohamed Shahim, Raju Datla, Abhilash Bharath Ghanore, Lava Kumar Bokam, Suresh Kumar Vennam, Rajashekar Reddy Ereddy
  • Publication number: 20210191765
    Abstract: A method for scheduling an artificial neural network includes: accessing a processor representation of a multicore processor comprising processor cores, direct memory access cores, and a cost model; and accessing a network structure defining a set of layers. The method also includes, for each layer in the set of layers: generating a graph based on the processor representation, the graph defining compute nodes, data transfer nodes, and edges representing dependencies between the compute nodes and the data transfer nodes; and generating a schedule for the layer based on the graph, the schedule assigning the compute nodes to the processor cores and assigning the data transfer nodes to the direct memory access cores. The method further includes aggregating the schedule for each layer in the set of layers to generate a complete schedule for the artificial neural network.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 24, 2021
    Inventors: Lava Kumar Bokam, Sameek Bannerjee, Abhilash Bharath Ghanore, Rajashekar Reddy Ereddy, Wajahat Qadeer, Rehan Hameed, Mohamed Shahim, Sreenivas Aerra Reddy
  • Patent number: 10445265
    Abstract: In one embodiment, a method includes receiving an input signal at a local data lane comprising a dynamic entry shift register, the input signal comprising a marker also received at a remote data lane, identifying receipt of the marker in the local data lane, starting a timer and notifying the remote data lane that the marker was found, receiving a marker found status from the remote data lane and saving a value of the timer, calculating a compensated delay for the remote data lane based on the timer value and a number of pipeline stages for the remote data lane, and setting an entry point to the dynamic entry shift register based on the compensated delay to deskew data between the local data lane and the remote data lane.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: October 15, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Matthew Todd Lawson, Lewis Leo Butler, II, Rajashekar Reddy Bussa
  • Patent number: 10379890
    Abstract: A controller coordinates execution of a set of related processes executed by respective devices in the virtual network, wherein coordinating comprises causing the respective devices to execute the set of related processes; receiving a data set for the set of related processes from the respective devices, comprising receiving operational states of the related processes from the respective devices; reading a previous data set comprising previous operational states of the related processes from the respective devices; processing an update to the previous operational states from the received operational states of the received data set; and aggregating the received operational states of the data set with the previous operational states of the related processes to form aggregated data of updated operational states.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 13, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Anish Mehta, Sundaresan Rajangam, Rajashekar Reddy, Megh Bhatt, Tirthankar Ghose
  • Publication number: 20190121758
    Abstract: In one embodiment, a method includes receiving an input signal at a local data lane comprising a dynamic entry shift register, the input signal comprising a marker also received at a remote data lane, identifying receipt of the marker in the local data lane, starting a timer and notifying the remote data lane that the marker was found, receiving a marker found status from the remote data lane and saving a value of the timer, calculating a compensated delay for the remote data lane based on the timer value and a number of pipeline stages for the remote data lane, and setting an entry point to the dynamic entry shift register based on the compensated delay to deskew data between the local data lane and the remote data lane.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 25, 2019
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Matthew Todd Lawson, Lewis Leo Butler, II, Rajashekar Reddy Bussa
  • Patent number: 9929911
    Abstract: In general, techniques are described in which a plurality of network switches automatically configure themselves to operate as a single virtual network switch. A virtual switch is a collection of individual switch devices that operate like as single network switch. As described herein, network switches in a network that are capable of participating in a virtual switch may automatically discover one another. The participating network switches may then elect one of the participating switches as a master switch. The master switch may generate forwarding information and store the forwarding information in the participating switches, including the master switch. The forwarding information causes the participating switches to act like a single network switch.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: March 27, 2018
    Assignee: Juniper Networks, Inc.
    Inventors: Rajashekar Reddy, Ankur Singla, Harshad Bhaskar Nakil, Pedro R. Marques, Ashish Ranjan
  • Patent number: 9710762
    Abstract: In general, techniques are described for dynamically modifying the extent of logging performed by logging information generators in response to events detected in logging information received by the collector. In some examples, a network device includes one or more processors and a collector executed by the processors to receive a log message that includes logging information from a generator. The network device also includes a rules engine to apply one or more rules that each specify a condition and a corresponding action to the logging information to identify a matching rule, wherein the rules engine, upon identifying a matching rule, executes the action of the matching rule to generate and send a logging modification message to increase an extent to which the generator generates logging information.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 18, 2017
    Assignee: Juniper Networks, Inc.
    Inventors: Harshad Bhaskar Nakil, Ankur Singla, Rajashekar Reddy
  • Patent number: 9606896
    Abstract: In one example, a controller device includes one or more network interfaces communicatively coupled to one or more devices of a virtual network, and a processor configured to determine, for the virtual network, a set of two or more related processes executed by respective devices in the virtual network, receive via the network interfaces data for the set of two or more related processes, and aggregate the data for the set of two or more related processes to form aggregated data for the set of two or more related processes.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: March 28, 2017
    Assignee: Juniper Networks, Inc.
    Inventors: Anish Mehta, Megh Bhatt, Rajashekar Reddy
  • Patent number: 9491089
    Abstract: A virtual device includes multiple devices connected to operate as a single device. A first one of the devices is configured to determine that the first device connects to a second one of the devices via a first link; identify a second link; determine that the second link connects the first device to the second device; and automatically aggregate the first link and the second link to form a link aggregation with the second device based on determining that the first device connects to the second device via both the first and second links. The first device is further configured to transmit packets to the second device via the first and second links of the link aggregation.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: November 8, 2016
    Assignee: Juniper Networks, Inc.
    Inventors: Megh Bhatt, Harshad Nakil, Rajashekar Reddy, Saurabh Agarwal, Sai Ganesh Sitharaman
  • Patent number: 9485194
    Abstract: Access switches in a switching system may use virtual aggregated links. When a link between an aggregation switch and an access switch fails, the link failure may be reflected in the virtual aggregated link and data traffic to another access switch may be switched away from the failed switch. A forwarding table in the access switch stores a number of entries that each define a correspondence between destination addresses and an output identifier for the switch. At least a first output identifier includes an aggregated link that represents a first set of possible output links. At least a second output identifier includes a virtual aggregated link, associated with a second network switch that represents a second set of possible output links. Destination addresses in the forwarding table for the virtual aggregated link correspond to network devices connected to the second network switch.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 1, 2016
    Assignee: Juniper Networks, Inc.
    Inventors: Ankur Singla, Harshad Nakil, Rajashekar Reddy, Hampapur Nagaraj Ajay