Patents by Inventor Rajat Agarwal
Rajat Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966286Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.Type: GrantFiled: April 7, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Kuljit S. Bains, Rajat Agarwal, Jongwon Lee
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Patent number: 11960900Abstract: Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.Type: GrantFiled: December 28, 2019Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Murugasamy K. Nachimuthu, Rajat Agarwal, Mohan J. Kumar
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Patent number: 11954111Abstract: Disclosed is system for executing service request. The system comprises a processing arrangement and data sources. The processing arrangement receives the service request and is configured to extract data from the data sources based on the service request. The data sources respond in response to a characteristic framework of the service request. The system further comprises an administrator module to permute the service request received by the processing arrangement in accordance with the characteristic framework employed by the data sources. The administrator module is configured to identify at least one attribute of the service request, obtain data corresponding to the at least one attribute of the service request from the data sources, normalize the obtained data and provide the normalized data to execute the service request, via the processing arrangement.Type: GrantFiled: March 29, 2019Date of Patent: April 9, 2024Assignee: INNOPLEXUS AGInventors: Ashwinkumar Rathod, Souymadeep Ghosh, Rohit Agarwal, Rajat Chaudhary
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Patent number: 11928124Abstract: An Artificial Intelligence (AI)-based data processing system processes current data to determine if the quality of the current data is adequate to be provided to data consumers and if the quality is adequate, the current data is further analyzed to determine if an impacted load including changes to dimension data of the current data or an incremental load including changes to fact data of the current data is to be provided to the data consumers. Depending on the amount of data to be provided to the data consumers, processing units (PUs) may be determined and assigned to carry out the data upload. Various machine learning (ML) models that are used to provide predictions from the current data are analyzed to determine the quality of predictions and if needed, can be automatically retrained by the data processing system.Type: GrantFiled: August 3, 2021Date of Patent: March 12, 2024Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITEDInventors: Mamta Aggarwal Rajnayak, Govindarajan Jothikumar, Rajat Agarwal, Prateek Jain
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Publication number: 20240061741Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.Type: ApplicationFiled: December 26, 2020Publication date: February 22, 2024Inventors: Rajat AGARWAL, Hsing-Min CHEN, Wei P. CHEN, Wei WU, Jing LING, Kuljit S. BAINS, Kjersten E. CRISS, Deep K. BUCH, Theodros YIGZAW, John G. HOLM, Andrew M. RUDOFF, Vaibhav SINGH, Sreenivas MANDAVA
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Publication number: 20240053904Abstract: The technology disclosed herein comprises a processor; a memory to store data and a plurality of error correcting code (ECC) bits associated with the data; and a memory controller coupled to the memory, the memory controller to receive a write request from the processor and, when an access control field is selected in the write request, perform an exclusive OR (XOR) operation on the plurality of ECC bits and a fixed encoding pattern to generate a plurality of encoded ECC bits and store the data and the plurality of encoded ECC bits in the memory.Type: ApplicationFiled: September 14, 2022Publication date: February 15, 2024Applicant: Intel CorporationInventors: Sergej Deutsch, David M. Durham, Karanvir Grewal, Rajat Agarwal
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Patent number: 11901299Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.Type: GrantFiled: December 12, 2022Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik, Ram S. Viswanath, Sandeep B. Sane, Sriram Srinivasan, Rajat Agarwal, Aravind Dasu, Scott Weber, Ravi Gutala
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Publication number: 20230400996Abstract: Some aspects of the present disclosure relate to an apparatus comprising interface circuitry and processor circuitry to write data bits to a memory, by applying a diffusion function on the data bits to calculate diffused data bits, calculating error correcting code (ECC) bits based on the data bits or based on the diffused data bits, applying a diffusion function on the ECC bits to calculate diffused ECC bits, storing the diffused ECC bits in an ECC portion of the memory, and storing the data bits or the diffused data bits in a data portion of the memory.Type: ApplicationFiled: June 13, 2023Publication date: December 14, 2023Inventors: Sergej DEUTSCH, David M. DURHAM, Karanvir GREWAL, Raghunandan MAKARAM, Rajat AGARWAL, Christoph DOBRAUNIG, Krystian MATUSIEWICZ, Santosh GHOSH
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MESSAGE AUTHENTICATION GALOIS INTEGRITY AND CORRECTION (MAGIC) FOR LIGHTWEIGHT ROW HAMMER MITIGATION
Publication number: 20230402077Abstract: The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.Type: ApplicationFiled: December 22, 2022Publication date: December 14, 2023Applicant: Intel CorporationInventors: Sergej Deutsch, Christoph Dobraunig, Rajat Agarwal, David M. Durham, Santosh Ghosh, Karanvir Grewal, Krystian Matusiewicz -
Patent number: 11837314Abstract: An embodiment of an electronic memory apparatus may include storage media, and logic communicatively coupled to the storage media, the logic to determine if a mode is set to one of a first mode or a second mode, perform a soft post package repair in the first mode, and undo the soft post package repair in the second mode. Other embodiments are disclosed and claimed.Type: GrantFiled: February 19, 2020Date of Patent: December 5, 2023Assignee: SK Hynix NAND Product Solutions Corp.Inventors: Bill Nale, Kuljit Bains, Wei Chen, Rajat Agarwal
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Publication number: 20230107106Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
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Publication number: 20230093247Abstract: An embodiment of an integrated circuit may comprise local memory, a plurality of per-page counters located in a non-system-addressable region of the local memory, and circuitry coupled to the local memory, the circuitry to count accesses to pages of a system-addressable memory space with the plurality of per-page counters located in the non-system-addressable region of the local memory. Other embodiments are disclosed and claimed.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: Intel CorporationInventors: Sanjay Kumar, Bhargavi Narayanasetty, Andrew Anderson, Anupama Kurpad, Evgeny V. Voevodin, Patrick Ndouniama, Sai Prashanth Muralidhara, Rajat Agarwal, Mohamed Arafa
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Publication number: 20230083193Abstract: A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.Type: ApplicationFiled: June 15, 2021Publication date: March 16, 2023Inventors: Shen ZHOU, Xiaoming DU, Cong LI, Kuljit S. BAINS, Rajat AGARWAL, Murugasamy K. NACHIMUTHU, Maciej LAWNICZAK, Chao Yan TANG, Mariusz ORIOL
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Publication number: 20230071117Abstract: A memory module has a registering clock driver (RCD) that issues two column address strobe (CAS) commands with a single memory access command to exchange a double amount of data per dynamic random access memory (DRAM) device per memory access command. With double the amount of data per DRAM device, the memory module can provide double the pseudo channels as compared to a memory module where a single CAS command is issued per access command. The RCD can time division multiplex separate first commands for a first group of the DRAM devices from second commands for a second group of the DRAM devices on the command/address (CA) bus.Type: ApplicationFiled: November 15, 2022Publication date: March 9, 2023Inventors: Hussein ALAMEER, Bill NALE, George VERGIS, Rajat AGARWAL
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Memory system, computing system, and methods thereof for cache invalidation with dummy address space
Patent number: 11580029Abstract: A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.Type: GrantFiled: April 6, 2021Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Andy Rudoff, Tiffany J. Kasanicky, Wei P. Chen, Rajat Agarwal, Chet R. Douglas -
Publication number: 20230039828Abstract: An Artificial Intelligence (AI)-based data processing system processes current data to determine if the quality of the current data is adequate to be provided to data consumers and if the quality is adequate, the current data is further analyzed to determine if an impacted load including changes to dimension data of the current data or an incremental load including changes to fact data of the current data is to be provided to the data consumers. Depending on the amount of data to be provided to the data consumers, processing units (PUs) may be determined and assigned to carry out the data upload. Various machine learning (ML) models that are used to provide predictions from the current data are analyzed to determine the quality of predictions and if needed, can be automatically retrained by the data processing system.Type: ApplicationFiled: August 3, 2021Publication date: February 9, 2023Applicant: ACCENTURE GLOBAL SOLUTIONS LIMITEDInventors: Mamta Aggarwal RAJNAYAK, Govindarajan JOTHIKUMAR, Rajat AGARWAL, Prateek JAIN
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Patent number: 11567877Abstract: An embodiment of a memory controller device includes technology to control access to a multi-level memory including at least a first level memory and a second level memory, provide direct access to the first level memory based on a system memory address, cache accesses to the second level memory in a second portion of the first level memory, and address a memory space with a total memory capacity which includes a first capacity of the first portion of the first level memory plus a second capacity of the second level memory. Other embodiments are disclosed and claimed.Type: GrantFiled: May 3, 2019Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Suresh S. Chittor, Rajat Agarwal, Wei P. Chen
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Patent number: 11557541Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.Type: GrantFiled: December 28, 2018Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik, Ram S. Viswanath, Sandeep B. Sane, Sriram Srinivasan, Rajat Agarwal, Aravind Dasu, Scott Weber, Ravi Gutala
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Publication number: 20220365885Abstract: Techniques are described for providing low-overhead cryptographic memory isolation to mitigate attack vulnerabilities in a multi-user virtualized computing environment. Memory read and memory write operations for target data, each operation initiated via an instruction associated with a particular virtual machine (VM), include the generation and/or validation of a message authentication code that is based at least on a VM-specific cryptographic key and a physical memory address of the target data. Such operations may further include transmitting the generated message authentication code via a plurality of ancillary bits incorporated within a data line that includes the target data. In the event of a validation failure, one or more error codes may be generated and provided to distinct trust domain architecture entities based on an operating mode of the associated virtual machine.Type: ApplicationFiled: July 25, 2022Publication date: November 17, 2022Applicant: Intel CorporationInventors: Siddhartha Chhabra, Rajat Agarwal, Baiju Patel, Kirk Yap
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Publication number: 20220350500Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.Type: ApplicationFiled: June 30, 2022Publication date: November 3, 2022Inventors: Wei P. CHEN, Theodros YIGZAW, Sarathy JAYAKUMAR, Anthony LUCK, Deep K. BUCH, Rajat AGARWAL, Kuljit S. BAINS, John G. HOLM, Brent CHARTRAND, Keith KLAYMAN