Patents by Inventor Rajat Agarwal

Rajat Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210216452
    Abstract: A two-level main memory in which both volatile memory and persistent memory are exposed to the operating system in a flat manner and data movement and management is performed in cache line granularity is provided. The operating system can allocate pages in the two-level main memory randomly across the first level main memory and the second level main memory in a memory-type agnostic manner, or, in a more intelligent manner by allocating predicted hot pages in first level main memory and predicted cold pages in second level main memory. The cache line granularity movement is performed in a “swap” manner, that is, a hot cache line in the second level main memory is swapped with a cold cache line in first level main memory because data is stored in either first level main memory or second level main memory not in both first level main memory and second level main memory.
    Type: Application
    Filed: March 27, 2021
    Publication date: July 15, 2021
    Inventors: Sai Prashanth MURALIDHARA, Alaa R. ALAMELDEEN, Rajat AGARWAL, Wei P. CHEN, Vivek KOZHIKKOTTU
  • Patent number: 11036634
    Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Wei Chen, Rajat Agarwal, Jing Ling, Daniel W. Liu
  • Patent number: 11030108
    Abstract: In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Berkin Akin, Rajat Agarwal, Jong Soo Park, Christopher J. Hughes, Chiachen Chou
  • Patent number: 11019098
    Abstract: The present disclosure is directed to systems and methods for providing protection against replay attacks on memory, by refreshing or updating encryption keys. The disclosed replay protected computing system may employ encryption refresh of memory so that unauthorized copies of data are usable for a limited amount of time (e.g., 500 milliseconds or less). The replay protected computing system initially encrypts protected data prior to storage in memory. After a predetermined time or after a number of memory accesses have occurred, the replay protected computing system decrypts the data with the existing key and re-encrypts data with a new key. Unauthorized copies of data (such as those made by an adversary system/program) are not refreshed with subsequent new keys. When an adversary program attempts to use the unauthorized copies of data, the unauthorized copies of data are decrypted with the incorrect keys, which renders the decrypted data unintelligible.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Sergej Deutsch, David Durham, Karanvir Grewal, Rajat Agarwal
  • Patent number: 11010304
    Abstract: A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Uksong Kang, Kjersten E. Criss, Rajat Agarwal, John B. Halbert
  • Publication number: 20210141692
    Abstract: A memory subsystem includes multiple memory resources connected in parallel, including a first memory resource and a second memory resource. The memory subsystem can split a portion of data into multiple sub-portions. Split into smaller portions, the system needs fewer ECC (error checking and correction) bits to provide the same level of ECC protection. The portion of data can include N ECC bits for error correction, and the sub-portions can each include a sub-portion of (N?M) ECC bits for error correction. The system can then use M bits of data for non-ECC purposes, such as metadata.
    Type: Application
    Filed: January 22, 2021
    Publication date: May 13, 2021
    Inventors: Rajat AGARWAL, Wei P. CHEN, Bill NALE, James A. McCALL
  • Patent number: 10997082
    Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: May 4, 2021
    Inventors: Andy Rudoff, Tiffany J. Kasanicky, Wei P. Chen, Rajat Agarwal, Chet R. Douglas
  • Patent number: 10963404
    Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: James A. McCall, Rajat Agarwal, George Vergis, Bill Nale
  • Patent number: 10901899
    Abstract: A processor includes a core to execute a transaction with a memory via cache; and cache controller having an index mapper circuit to: identify a physical memory address associated with the transaction and having a plurality of bits; determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value; determine a mapping function corresponding to the tag value; determine, using the mapping function, a bit-placement order; combine, based on the order, second and third set of bits to form an index; generate, using the index, a mapping from the address to a cache line index value identifying a cache line in the cache; and wherein the cache controller is further to access, using the mapping and in response to the transaction, the cache line.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Ruchira Sasanka, Rajat Agarwal
  • Patent number: 10884958
    Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Rajat Agarwal, Bill Nale, Chong J. Zhao, James A. McCall, George Vergis
  • Patent number: 10877897
    Abstract: In one embodiment, a method includes: in response to a sub-cacheline memory access request, receiving a data-line from a memory coupled to a processor; receiving tag information included in metadata associated with the data-line from the memory; determining, in a memory controller, whether a first tag identifier of the tag information matches a tag portion of an address of the memory line associated with the sub-cacheline memory access request, and in response to determining a match, storing a first portion of the data-line associated with the first tag identifier in a cache line of a cache of the processor, the first portion a sub-cacheline width. This method allows data lines stored in memory associated with multiple different tag metadata to be divided into multiple cachelines comprising the sub-cacheline data associated with a particular metadata address tag. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: David M. Durham, Ron Gabor, Rajat Agarwal
  • Patent number: 10872011
    Abstract: A memory subsystem includes a data bus to couple a memory controller to one or more memory devices. The memory controller and one or more memory devices transfer data for memory access operations. The data transfer includes the transfer of data bits and associated check bits over a transfer cycle burst. The memory devices include internal error checking and correction (ECC) separate from the system ECC managed by the memory controller. With a 2N transfer cycle for 2{circumflex over (?)}N data bits for a memory device, the memory devices can provide up to 2N memory locations for N+1 internal check bits, which can leave up to (2N minus (N+1)) extra bits to be used by the system for more robust ECC.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, Bill Nale, Rajat Agarwal
  • Publication number: 20200278906
    Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Inventors: Kuljit S. BAINS, Rajat AGARWAL, Jongwon LEE
  • Patent number: 10725861
    Abstract: System and techniques for error correction code (ECC) memory security are described herein. A write request that includes data is received. An integrity check value (ICV) is computed for the data. Then, the write request is performed, including writing a representation of the data to a data area in memory and writing the ICV into an ECC area in memory. Here, the data area is addressable by a host and the ECC area corresponds to the data area via hardware of the memory.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Anatoli Bolotov, Mikhail Grinchuk, Rajat Agarwal
  • Patent number: 10719443
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20200201787
    Abstract: A processor includes a processor core to execute an application; a key attribute table (KAT) register to store a plurality of key identifiers (KeyIDs) associated with the application, wherein a KeyID identifies an encryption key; a selection circuit coupled to the KAT register to select the KeyID from the KAT register based on a KeyID selector (KSEL), wherein the KSEL is associated with a page of memory to which access is performed; a cache coupled to the processor core, the cache to store a physical address, data, and the KeyID of the page of memory, wherein the KeyID is an attribute associated with the page of memory; and a memory controller coupled to the cache to encrypt, based on the encryption key identified by the KeyID, the data of the page of memory stored in the cache as it is evicted from the cache to main memory.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: Vedvyas Shanbhogue, Stephen R. Van Doren, Gilbert Neiger, Barry E. Huntley, Amy Santoni, Raghunandan Makaram, Rajat Agarwal, Ronald Perez, Hormuzd Khosravi, Manjula Peddireddy, Siddhartha Chhabra
  • Publication number: 20200185052
    Abstract: An embodiment of an electronic memory apparatus may include storage media, and logic communicatively coupled to the storage media, the logic to determine if a mode is set to one of a first mode or a second mode, perform a soft post package repair in the first mode, and undo the soft post package repair in the second mode. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 11, 2020
    Applicant: Intel Corporation
    Inventors: Bill Nale, Kuljit Bains, Wei Chen, Rajat Agarwal
  • Publication number: 20200177392
    Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.
    Type: Application
    Filed: November 20, 2019
    Publication date: June 4, 2020
    Inventors: David M. Durham, Rajat Agarwal, Siddhartha Chhabra, Sergej Deutsch, Karanvir S. Grewal, Ioannis T. Schoinas
  • Publication number: 20200133683
    Abstract: Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.
    Type: Application
    Filed: December 28, 2019
    Publication date: April 30, 2020
    Inventors: Murugasamy K. Nachimuthu, Rajat Agarwal, Mohan J. Kumar