Patents by Inventor Rajat Aggarwal

Rajat Aggarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210209555
    Abstract: A system and method for determining collaboration metrics of an application is described. The system accesses user activity data of an application from a plurality of user accounts of an enterprise. Collaboration metrics for each user account are identified based on the corresponding user activity data. The system identifies a first group and a second group of user accounts from the plurality of user accounts. The system generates a recommendation of a configuration setting of the application for the second group of user accounts. A graphical user interface (GUI) indicates the first group and the second group of user accounts, and the recommendation of the configuration setting of the application for the second group of user accounts.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 8, 2021
    Inventors: Sanjay Hemmige Ramaswamy, Patri Venkata Raghu Chandra Subhash, Siddarth Rajendra Kumar, Bhavatarini Mallikarjuna Pushpa, V. S. Srujana Oruganti, Prasanth Sri Kara, Sreeram Nivarthi, Abhishek Kalai Raghavendra, Jagadeesh Virupaksha Huliyar, Tapas Bansal, Amit Ramakant Patil, Rajat Aggarwal
  • Patent number: 11025888
    Abstract: A system for capturing Omni-Stereo videos using multi-sensor includes left cameras, right cameras and a viewing circle. A method of capturing omni stereo videos using multi-sensor approach includes steps of: capturing images of a scene using left cameras, capturing images of a scene using right cameras, processing each image from the left camera and right camera using a computation method, and obtaining a final omni stereo frame through the computation method.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 1, 2021
    Assignee: DreamVu, Inc.
    Inventors: Rajat Aggarwal, Anoop M. Namboodiri
  • Patent number: 10995377
    Abstract: The present subject matter relates to methods and compositions for identifying soybean plants that having increased Phytophthora root and stem rot resistance. The methods use molecular markers to identify and to select plants with increased Phytophthora root and stem rot resistance or to identify and deselect plants with decreased Phytophthora root and stem rot resistance. Soybean plants generated by the methods disclosed are also a feature of the present subject matter.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: May 4, 2021
    Assignees: CORTEVA AGRISCIENCE LLC
    Inventors: Jianxin Ma, Jieqing Ping, Joshua C. Fitzgerald, Chunbao Zhang, Feng Lin, Yonghe Bai, Maqsood Rehman, Oswald Crasta, Rajat Aggarwal, Ananta Acharya
  • Publication number: 20210112493
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit a message including an indication that the UE is in a power-saving mode. The UE may receive a configuration, for a connected state of the UE, that is based at least in part on the indication. The UE may operate in the connected state according to the configuration. Numerous other aspects are provided.
    Type: Application
    Filed: October 5, 2020
    Publication date: April 15, 2021
    Inventors: Neel Tej Adusumilli, Ethan IDENMILL, Ozcan OZTURK, Rajat AGGARWAL
  • Publication number: 20200068823
    Abstract: The present invention relates to methods for identifying sunflower lines having increased resistance to Verticillium wilt, and identification of genetic markers linked to gene(s) conditioning such increased disease resistance.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 5, 2020
    Inventors: Rajat Aggarwal, Martin Ariel Cantore, Natalia Mercedes Paz
  • Patent number: 10477788
    Abstract: The present invention relates to methods for identifying sunflower lines having increased resistance to Verticillium wilt, and identification of genetic markers linked to gene(s) conditioning such increased disease resistance. The present invention also relates to methods of breeding sunflower plants from lines having increased Verticillium wilt resistance by marker-assisted selection, compositions including nucleic acid probes or primers which are useful for such marker assisted selection, and plants and plant parts produced by such methods.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: November 19, 2019
    Assignee: Agrigenetics, Inc.
    Inventors: Rajat Aggarwal, Martin Ariel Cantore, Natalia Mercedes Paz
  • Publication number: 20190349567
    Abstract: A system and method for capturing Omni-Stereo videos using multi-sensor is disclosed. The system includes left cameras, right cameras and a viewing circle. The method of capturing omni stereo videos using multi-sensor approach includes steps of: capturing images of a scene using left cameras, capturing images of a scene using right cameras, processing each image from the left camera and right camera using a computation method, and obtaining a final omni stereo frame through the computation method.
    Type: Application
    Filed: February 15, 2019
    Publication date: November 14, 2019
    Inventors: Rajat Aggarwal, Anoop M. Namboodiri
  • Patent number: 10154249
    Abstract: A system for capturing horizontal disparity stereo panorama is disclosed. The system includes a multi surface selective light reflector unit, a secondary reflector and a computing unit. The multi surface selective light reflector unit (a) obtains light rays from a 3D scene of outside world that are relevant to create (i) a left eye panorama and (ii) a right eye panorama and (b) reflects the light rays without internal reflections between the light rays. The secondary reflector (a) obtains the reflected light rays from the multi surface selective light reflector unit and (b) reflects the light rays through the viewing aperture. The computing unit captures (i) the reflected light rays from the secondary reflector and (ii) the upper part of the 3D scene from a concave lens as a warped image and processes the warped image to (a) the left eye panorama and (b) the right eye panorama.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 11, 2018
    Inventors: Anoop M Namboodiri, Rajat Aggarwal, Amrisha Vohra
  • Publication number: 20180030550
    Abstract: The present subject matter relates to methods and compositions for identifying soybean plants that having increased Phytophthora root and stem rot resistance. The methods use molecular markers to identify and to select plants with increased Phytophthora root and stem rot resistance or to identify and deselect plants with decreased Phytophthora root and stem rot resistance. Soybean plants generated by the methods disclosed are also a feature of the present subject matter.
    Type: Application
    Filed: June 2, 2016
    Publication date: February 1, 2018
    Applicants: Dow AgroSciences LLC, Purdue Research Foundation
    Inventors: Jianxin Ma, Jieqing Ping, Joshua C. Fitzgerald, Chunbao Zhang, Feng Lin, Yonghe Bai, Maqsood Rehman, Oswald Crasta, Rajat Aggarwal, Ananta Acharya
  • Publication number: 20170366800
    Abstract: A system for capturing horizontal disparity stereo panorama is disclosed. The system includes a multi surface selective light reflector unit, a secondary reflector and a computing unit. The multi surface selective light reflector unit (a) obtains light rays from a 3D scene of outside world that are relevant to create (i) a left eye panorama and (ii) a right eye panorama and (b) reflects the light rays without internal reflections between the light rays. The secondary reflector (a) obtains the reflected light rays from the multi surface selective light reflector unit and (b) reflects the light rays through the viewing aperture. The computing unit captures (i) the reflected light rays from the secondary reflector and (ii) the upper part of the 3D scene from a concave lens as a warped image and processes the warped image to (a) the left eye panorama and (b) the right eye panorama.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 21, 2017
    Inventors: Anoop M. Namboodiri, Rajat Aggarwal, Amrisha Vohra
  • Publication number: 20170303486
    Abstract: This invention relates to methods for identifying maize plants that having increased culturability and/or transformability. The methods use molecular markers to identify and to select plants with increased culturability and/or transformability or to identify and deselect plants with decreased culturability and/or transformability. Maize plants generated by the methods of the invention are also a feature of the invention.
    Type: Application
    Filed: October 9, 2015
    Publication date: October 26, 2017
    Applicant: Dow AgroSciences LLC
    Inventors: Tristan E. Coram, Susan M. Jayne, Diaa Alabed, Stephen Foulk, Rajat Aggarwal, Natae Daniels
  • Patent number: 9723216
    Abstract: A method for generating images. The method includes capturing first image data representing a first scene taken optically at a first magnification index, wherein the first image data comprises a first region of an image. The method includes capturing second image data representing a second scene taken optically at a second magnification index that is less than the first magnification index, wherein the second image data comprises a second region of the image. The method includes digitally zooming the second image data in the second region to the first magnification index. The method includes digitally stitching the second image data in the second region to the first image data in the first region.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: August 1, 2017
    Assignee: NVIDIA CORPORATION
    Inventor: Rajat Aggarwal
  • Publication number: 20170098024
    Abstract: A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.
    Type: Application
    Filed: October 1, 2015
    Publication date: April 6, 2017
    Applicant: Xilinx, Inc.
    Inventors: Rajat Aggarwal, Zhiyong Wang, Ruibing Lu, Sabyasachi Das
  • Patent number: 9613173
    Abstract: A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: April 4, 2017
    Assignee: XILINX, INC.
    Inventors: Rajat Aggarwal, Zhiyong Wang, Ruibing Lu, Sabyasachi Das
  • Publication number: 20160150747
    Abstract: The present invention relates to methods for identifying sunflower lines having increased resistance to Verticillium wilt, and identification of genetic markers linked to gene(s) conditioning such increased disease resistance. The present invention also relates to methods of breeding sunflower plants from lines having increased Verticillium wilt resistance by marker-assisted selection, compositions including nucleic acid probes or primers which are useful for such marker assisted selection, and plants and plant parts produced by such methods.
    Type: Application
    Filed: November 19, 2015
    Publication date: June 2, 2016
    Inventors: Rajat Aggarwal, Martin Ariel Cantore, Natalia Mercedes Paz
  • Publication number: 20150229848
    Abstract: A method for generating images. The method includes capturing first image data representing a first scene taken optically at a first magnification index, wherein the first image data comprises a first region of an image. The method includes capturing second image data representing a second scene taken optically at a second magnification index that is less than the first magnification index, wherein the second image data comprises a second region of the image. The method includes digitally zooming the second image data in the second region to the first magnification index. The method includes digitally stitching the second image data in the second region to the first image data in the first region.
    Type: Application
    Filed: February 13, 2014
    Publication date: August 13, 2015
    Applicant: NVIDIA Corporation
    Inventor: Rajat AGGARWAL
  • Publication number: 20150159228
    Abstract: This invention relates to methods for identifying maize plants that having increased culturability and transformability. The methods use molecular markers to identify and to select plants with increased culturability and transformability. Maize plants generated by the methods of the invention are also a feature of the invention.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 11, 2015
    Inventors: Tristan E. Coram, Diaa Alabed, Susan M. Jayne, Stephen Foulk, Rajat Aggarwal, Natae Daniels
  • Patent number: 8448122
    Abstract: A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: May 21, 2013
    Assignee: Xilinx, Inc.
    Inventors: Vishal Suthar, Hasan Arslan, Sridhar Krishnamurthy, Sanjeev Kwatra, Srinivasan Dasasathyan, Rajat Aggarwal, Sudip K. Nag
  • Patent number: 8418115
    Abstract: A method of component placement for a multi-die integrated circuit (IC) can include partitioning a plurality of components of a netlist among a plurality of dies of the multi-die IC and selecting a superimposition model specifying a positioning of at least two of the plurality of dies at least partially superimposed with respect to one another. The method also can include assigning, by a processor, components of the netlist to hardware units within each of the plurality of dies according, at least in part, to a wire-length metric calculated using the superimposition model.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: April 9, 2013
    Assignee: Xilinx, Inc.
    Inventors: Marvin Tom, Rajat Aggarwal, Srinivasan Dasasathyan
  • Patent number: 8312405
    Abstract: A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: November 13, 2012
    Assignee: Xilinx, Inc.
    Inventors: Victor Slonim, Rajat Aggarwal, Guenter Stenz, Srinivasan Dasasathyan