Abstract: A media integration layer including an application programming interface (API) and an object model allows program code developers to interface in a consistent manner with a scene graph data structure in order to output graphics. Via the interfaces, program code adds child visuals to other visuals to build up a hierarchical scene graph, writes Instruction Lists such as geometry data, image data, animation data and other data for output, and may specify transform, clipping and opacity properties on visuals. The media integration layer and API enable programmers to accomplish composition effects within their applications in a straightforward manner, while leveraging the graphics processing unit in a manner that does not adversely impact normal application performance. A multiple-level system includes the ability to combine different media types (such as 2D, 3D, Video, Audio, text and imaging) and animate them smoothly and seamlessly.

Abstract: An improved system and method for an extensible codec architecture for digital images is provided. Executable software code may be operably coupled to a codec manager for requesting imaging operations to be performed on a digital image. The codec manager may receive the request to perform an imaging operation on the digital image and may select an imaging component, such as a codec, from one or more imaging components registered in the computer system for performing an imaging operation on the digital image. An arbitration manager may include functionality for requesting enumeration of the operations an imaging component may perform on a particular digital image. One or more pixel format converters may then convert the pixel format in the digital image to a pixel format supported by an imaging component installed on the system.

Abstract: In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are being retired, the compare circuitry is configured to detect a match between at least a first identifier in a first storage location and one of the retiring identifiers. An encoded form of the identifiers is logically divided into a plurality of fields, and the input comprises a first plurality of bit vectors. Each of the first plurality of bit vectors corresponds to a respective field and includes a bit position for each possible value of the respective field.

Abstract: Various embodiments are disclosed relating to providing multiple and native representations of an image. According to an example embodiment, multiple realizations of an image may be generated and provided, rather than only a single realization, for example. Also, in another embodiment, the generation and output of multiple realizations may use one or more native objects to natively perform the transforms or image processing to provide the images or realizations.

Abstract: In one embodiment, a memory circuit comprises one or more first memory cells, each of the one or more first memory cells configured to store at least one bit; one or more second memory cells, each of the one or more second memory cells configured to store at least one bit; and one or more read port circuits physically located between the first memory cells and the second memory cells. Each of the read port circuits is coupled to receive the at least one bit from each of the first memory cells and each of the second memory cells, and each of the read port circuits is configured to output the at least one bit from a selected memory cell of the first memory cells and the second memory cells responsive to a plurality of wordline signals coupled to the read port circuit.

Abstract: In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.

Abstract: In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.

Abstract: In aspects, a class hierarchy is defined that provides definitions of methods for operating on at least bitmaps and vector graphics. A software developer may instantiate an object according to a class definition of the class hierarchy and assign it to any variable (e.g., a control's property) having a type of an ancestor class of the class. The object may be associated with an image internally represented as bitmap, vector graphics, or some other representation. The control does not need to be aware of how the image is represented. Rather, to draw an image associated with the object, a draw method associated with the object may be called.

Abstract: In one embodiment, a read port circuit includes a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsive to a first plurality of wordline signals and a first plurality of data signals. Each of the wordline signals corresponds to a respective memory cell of a first plurality of memory cells, and each of the data signals corresponds to a respective memory cell and represents data stored in the respective memory cell. In some embodiments, the read port circuit may be included in a register file in an integrated circuit that also includes logic circuitry configured to generate an address for a read port.

Abstract: In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are being retired, the compare circuitry is configured to detect a match between at least a first identifier in a first storage location and one of the retiring identifiers. An encoded form of the identifiers is logically divided into a plurality of fields, and the input comprises a first plurality of bit vectors. Each of the first plurality of bit vectors corresponds to a respective field and includes a bit position for each possible value of the respective field.

Abstract: In one embodiment, a memory circuit comprises one or more first memory cells, each of the one or more first memory cells configured to store at least one bit; one or more second memory cells, each of the one or more second memory cells configured to store at least one bit; and one or more read port circuits physically located between the first memory cells and the second memory cells. Each of the read port circuits is coupled to receive the at least one bit from each of the first memory cells and each of the second memory cells, and each of the read port circuits is configured to output the at least one bit from a selected memory cell of the first memory cells and the second memory cells responsive to a plurality of wordline signals coupled to the read port circuit.

Abstract: In one embodiment, a read port circuit comprises a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsive to a first plurality of wordline signals and a first plurality of data signals. Each of the wordline signals corresponds to a respective memory cell of a first plurality of memory cells, and each of the data signals corresponds to a respective memory cell and represents data stored in the respective memory cell. In some embodiments, the read port circuit may be included in a register file in an integrated circuit that also comprises logic circuitry configured to generate an address for a read port.

Abstract: An improved system and method for an extensible codec architecture for digital images is provided. Executable software code may be operably coupled to a codec manager for requesting imaging operations to be performed on a digital image. The codec manager may receive the request to perform an imaging operation on the digital image and may select an imaging component, such as a codec, from one or more imaging components registered in the computer system for performing an imaging operation on the digital image. An arbitration manager may include functionality for requesting enumeration of the operations an imaging component may perform on a particular digital image. One or more pixel format converters may then convert the pixel format in the digital image to a pixel format supported by an imaging component installed on the system.

Abstract: An improved system and method for an extensible metadata architecture for digital images is provided. Executable software code may be operably coupled to a metadata query reader and a metadata query writer for requesting operations for manipulating metadata in an image file. The metadata query reader may be operably coupled to a decoder having a block reader for identifying metadata blocks in an image file and associating a metadata reader with each metadata block. Each metadata reader may then enumerate the metadata in the metadata block associated with that metadata reader. The metadata query writer may be operably coupled to an encoder having a block writer for associating a metadata writer with each metadata block to be written to an image file. Each metadata writer may then write metadata in the metadata block associated with that metadata writer.

Abstract: An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.

Abstract: An improved system and method for an extensible metadata architecture for digital images is provided. Executable software code may be operably coupled to a metadata query reader and a metadata query writer for requesting operations for manipulating metadata in an image file. The metadata query reader may be operably coupled to a decoder having a block reader for identifying metadata blocks in an image file and associating a metadata reader with each metadata block. Each metadata reader may then enumerate the metadata in the metadata block associated with that metadata reader. The metadata query writer may be operably coupled to an encoder having a block writer for associating a metadata writer with each metadata block to be written to an image file. Each metadata writer may then write metadata in the metadata block associated with that metadata writer.

Abstract: A media integration layer including an application programming interface (API) and an object model allows program code developers to interface in a consistent manner with a scene graph data structure in order to output graphics. Via the interfaces, program code adds child visuals to other visuals to build up a hierarchical scene graph, writes Instruction Lists such as geometry data, image data, animation data and other data for output, and may specify transform, clipping and opacity properties on visuals. The media integration layer and API enable programmers to accomplish composition effects within their applications in a straightforward manner, while leveraging the graphics processing unit in a manner that does not adversely impact normal application performance. A multiple-level system includes the ability to combine different media types (such as 2D, 3D, Video, Audio, text and imaging) and animate them smoothly and seamlessly.