Patents by Inventor Rajat Kohli

Rajat Kohli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250124976
    Abstract: A memory includes at least one memory bank which includes a set of memory arrays. Each memory cell includes a plurality of memory cells. The at least one memory bank includes: multiple word lines each connected to a corresponding row of the memory cells; a first decoder configured to receive address data, and decode the address data to provide intermediate data; a second decoder located in a central area of the memory bank between ones of the set of memory arrays, and configured to receive the intermediate data from the first decoder, and decode the intermediate data to provide selection data to the word lines. Memory cells addressable by a respective word line designated by the selection data are configured to be addressable by means of that selection data.
    Type: Application
    Filed: September 23, 2024
    Publication date: April 17, 2025
    Inventors: Jainendra Singh, Rajat Kohli, Ganesh Bhat, Jwalant Kumar Mishra
  • Publication number: 20240203480
    Abstract: A memory power control unit, MPCU, is provided for preventing unauthorised access to data stored in a volatile memory, the MPCU comprising a power controller comprising an input configured to receive a signal from a tamper detection circuit, a first supply input configured 5 to receive a first supply voltage, a first reference input configured to receive a first reference voltage, a supply output configured to output a supply voltage to the volatile memory, a reference output configured to output a reference voltage to the volatile memory, wherein, in response to receipt of a signal at the input indicative of an attempt to tamper with the volatile memory, the power controller is configured to output a reduced supply voltage via the supply 10 output for a first predetermined time period, wherein the reduced supply voltage is less than the first supply voltage.
    Type: Application
    Filed: December 11, 2023
    Publication date: June 20, 2024
    Inventors: Prokash Ghosh, Jyotirmoy Ghosh, Glenn Charles Abeln, Dwarka Prasad, Rajat Kohli, Jainendra Singh, Jwalant Kumar Mishra
  • Patent number: 10236071
    Abstract: A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.
    Type: Grant
    Filed: September 10, 2017
    Date of Patent: March 19, 2019
    Assignee: NXP B.V.
    Inventors: Rajat Kohli, Patrick Van De Steeg, Jwalant Kumar Mishra, Pankaj Agarwal
  • Publication number: 20190080777
    Abstract: A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.
    Type: Application
    Filed: September 10, 2017
    Publication date: March 14, 2019
    Inventors: Rajat Kohli, Patrick Van de Steeg, Jwalant Kumar Mishra, Pankaj Agarwal
  • Patent number: 9691496
    Abstract: Disclosed is a ROM memory including a first bitcell including a transistor to store two bits and first and second bit lines to read data stored in the bitcell, a second bitcell including a second transistor connected to the first transistor and sharing the first and second bit lines, and a virtual ground line adjacent the bit lines configured to ground the bitcells.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: June 27, 2017
    Assignee: NXP B.V.
    Inventors: Rajat Kohli, Patrick van de Steeg, Jwalant Kumar Mishra, Pankaj Agarwal
  • Patent number: 9202588
    Abstract: Disclosed is a ROM memory device including a plurality of rows and columns of memory cells, each memory cell including a bit line pair and a transistor to store two bits of data therein, and a virtual ground line disposed between adjacent pairs of bit line pairs, wherein the bit line pair and virtual ground line are used to read data stored in the memory cells.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: December 1, 2015
    Assignee: NXP B.V.
    Inventors: Rajat Kohli, Patrick Van de steeg, Jwalant Mishra, Pankaj Agarwal