Patents by Inventor Rajat Kohli

Rajat Kohli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual-bit ROM cell with virtual ground line and programmable metal track
    Patent number: 10236071
    Abstract: A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.
    Type: Grant
    Filed: September 10, 2017
    Date of Patent: March 19, 2019
    Assignee: NXP B.V.
    Inventors: Rajat Kohli, Patrick Van De Steeg, Jwalant Kumar Mishra, Pankaj Agarwal
  • DUAL-BIT ROM CELL WITH VIRTUAL GROUND LINE AND PROGRAMMABLE METAL TRACK
    Publication number: 20190080777
    Abstract: A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.
    Type: Application
    Filed: September 10, 2017
    Publication date: March 14, 2019
    Inventors: Rajat Kohli, Patrick Van de Steeg, Jwalant Kumar Mishra, Pankaj Agarwal
  • High density ROM cell with dual bit storage for high speed and low voltage
    Patent number: 9691496
    Abstract: Disclosed is a ROM memory including a first bitcell including a transistor to store two bits and first and second bit lines to read data stored in the bitcell, a second bitcell including a second transistor connected to the first transistor and sharing the first and second bit lines, and a virtual ground line adjacent the bit lines configured to ground the bitcells.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: June 27, 2017
    Assignee: NXP B.V.
    Inventors: Rajat Kohli, Patrick van de Steeg, Jwalant Kumar Mishra, Pankaj Agarwal
  • 1T compact ROM cell with dual bit storage for high speed and low voltage
    Patent number: 9202588
    Abstract: Disclosed is a ROM memory device including a plurality of rows and columns of memory cells, each memory cell including a bit line pair and a transistor to store two bits of data therein, and a virtual ground line disposed between adjacent pairs of bit line pairs, wherein the bit line pair and virtual ground line are used to read data stored in the memory cells.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: December 1, 2015
    Assignee: NXP B.V.
    Inventors: Rajat Kohli, Patrick Van de steeg, Jwalant Mishra, Pankaj Agarwal