Patents by Inventor Rajat Mehrotra
Rajat Mehrotra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11821945Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: GrantFiled: March 30, 2021Date of Patent: November 21, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Rajesh Kumar Mittal, Rajat Mehrotra
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Publication number: 20210215757Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: ApplicationFiled: March 30, 2021Publication date: July 15, 2021Inventors: Prakash Narayanan, Rajesh Kumar Mittal, Rajat Mehrotra
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Patent number: 10983161Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: GrantFiled: April 10, 2019Date of Patent: April 20, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Rajesh Kumar Mittal, Rajat Mehrotra
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Patent number: 10460821Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.Type: GrantFiled: February 14, 2018Date of Patent: October 29, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
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Publication number: 20190235020Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: ApplicationFiled: April 10, 2019Publication date: August 1, 2019Inventors: Prakash Narayanan, Rajesh Kumar Mittal, Rajat Mehrotra
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Patent number: 10274538Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: GrantFiled: October 2, 2017Date of Patent: April 30, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Publication number: 20180174663Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.Type: ApplicationFiled: February 14, 2018Publication date: June 21, 2018Inventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
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Patent number: 9899103Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.Type: GrantFiled: February 16, 2017Date of Patent: February 20, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
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Publication number: 20180045778Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: ApplicationFiled: October 2, 2017Publication date: February 15, 2018Inventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Publication number: 20170315174Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Patent number: 9791505Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: GrantFiled: April 29, 2016Date of Patent: October 17, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Publication number: 20170157524Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Inventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
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Publication number: 20170125125Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit of the system-on-a-chip (SoC) type. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.Type: ApplicationFiled: March 10, 2016Publication date: May 4, 2017Inventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
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Patent number: 9263147Abstract: An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.Type: GrantFiled: September 18, 2014Date of Patent: February 16, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajat Mehrotra, Rubin Ajit Parekhji, Maheedhar Jalasutram, Charu Shrimali
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Publication number: 20150325308Abstract: An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.Type: ApplicationFiled: September 18, 2014Publication date: November 12, 2015Applicant: Texas Instruments IncorporatedInventors: Rajat Mehrotra, Rubin Ajit Parekhji, Maheedhar Jalasutram, Charu Shrimali