Abstract: An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; and a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein. The thin third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å. A first layer of metal interconnects is formed over the thin third dielectric layer.

Abstract: A local interconnect for an integrated circuit structure is described capable of bridging over a conductive element to electrically connect together, at the local interconnect level, non-adjacent conductive portions of the integrated circuit structure. After formation of active devices and a conductive element of an integrated circuit structure in a semiconductor substrate, a silicon oxide mask is formed over the structure, with the conductive element covered by the silicon oxide mask. Metal silicide is then formed in exposed silicon regions beneath openings in the mask. The portion of the silicon oxide mask covering the conductive element is then retained as insulation. A silicon nitride etch stop layer and a planarizable dielectric layer are then formed over the structure. An opening is then formed through such silicon nitride and dielectric layers over the conductive element and exposed metal silicide regions adjacent the conductive element.

Abstract: An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; and a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein. The thin third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å. A first layer of metal interconnects is formed over the thin third dielectric layer.

Abstract: An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; and a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein. The thin third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å. A first layer of metal interconnects is formed over the thin third dielectric layer.

Abstract: Submicron nLDD CMOS logic devices with improved current drive and reduced reverse short-channel effects having heavily doped As and lightly doped P nLDD region.

Abstract: A method to monitor boron penetration and optimize process parameters in the fabrication of a semiconductor device have an n.sup.+ or a p.sup.- -polysilicon gate. The charge-to-breakdown Q.sub.BD value is used to monitor the boron penetration into the polysilicon/gate oxide interface. Values of Q.sub.BD for various values of process parameters are determined and optimized values for these process parameters are derived.

Abstract: A method of manufacturing a semiconductor device with reduced hot-carrier induced degradation wherein a nitrogen species is introduced into the gate oxide layer. The introduction of the nitrogen species may be done after the gate etch, after the spacer material deposition, or after the spacer etch. The nitrogen species may also be introduced into the gate oxide after both the gate etch and the spacer material deposition or after both the gate etch and the spacer etch or after all three steps.

Abstract: A method and circuit for detecting boron at an interface between a p-type polysilicon gate and silicon dioxide gate dielectric is provided. A V.sub.t fluence test using about -6.67 mA/cm.sup.2 is used to detect boron at the interface. A p-channel metal oxide semiconductor ("PMOS") device having a source, drain, substrate, gate and silicon dioxide layer are connected to ground and a current source in order to detect the boron. An about -6.67 mA/cm.sup.2 current is applied to the PMOS gate while the source, substrate and drain are grounded. Various changes in threshold voltages are observed over different stress times. The boron concentration at the polysilicon/gate dielectric interface has been detected by the shift in threshold voltage. The concentration of boron at the interface has been found to degrade oxide quality as evidenced by charge-to-breakdown ("Q.sub.BD ") test of the oxide.

Abstract: The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased.

Abstract: The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased.

Abstract: An improved process is provided for fabricating short channel complementary metal oxide semiconductor devices. The devices comprise source and drain regions separated by gate regions. The process comprises forming a shallow channel doping region (12') beneath the surface of a semiconductor (10) and forming source-drain regions (20') of opposite conductivity type (formerly known as lightly doped drain structures) on either side of the shallow doping region. A gate oxide (16) is formed on the surface of the semiconductor above the shallow channel doping region and a gate electrode (18) is formed to the gate oxide subsequent to the formation of the shallow channel doping region. The process permits spacing of the channel doping from the source-drain doping with self-alignment. Further, the doping of the source-drain regions is not constrained to the values of the lightly-doped structures of the prior art.