Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Abstract: Cryptographic-related processing is facilitated by obtaining multiple input operands, and packing the multiple input operands together to form a packed integer. The packed integer is an n-bit integer including multiple slots, where input operands of the multiple input operands are packed into every other slot of the multiple slots, and each slot of the multiple slots has a bitwidth k. Further, the process includes providing the packed integer as input to an n-bit accelerator to facilitate performing one or more predefined operations using the packed integer, to transform the packed integer into result data which facilitates cryptographic-related processing.

Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Abstract: Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer.

Abstract: Cryptographic-related processing is performed using an n-bit accelerator. The processing includes providing a binary operand to a multiply-and-accumulate unit of the n-bit accelerator. The multiply-and-accumulate unit performs an operation using the binary operand and a predetermined fractional constant F to obtain an operation result, and rounds the operation result by discarding x least-significant bits of the operation result to obtain a fractionally-scaled result, where x is a configurable number of bits to discard from the operation result, and the fractionally-scaled result facilitates performing the cryptographic-related processing.

Abstract: A method for transcoding an encoded video stream uploaded to a host server that includes a video transcoding engine connected to the server. At least one processor of the video transcoding engine receives an encoded video stream from a client computing device in which the encoded video stream is directly received by the video transcoding engine connected to the host server and the video transcoding engine has direct access to a non-volatile memory of the host server. The at least one processor of the video transcoding engine generates one or more transcoded files in real-time from the encoded video stream. The at least one processor transfers the one or more transcoded video files from the video transcoding engine directly to the non-volatile memory of the host server.

Abstract: Embodiments are directed to selecting a multiplication operation to be scheduled in a first stage of an execution schedule, the multiplication operation meeting a first condition of having no dependency. An addition/subtraction operation is selected to be scheduled in the first stage of the execution schedule responsive to meeting the first condition. A process is performed which includes selecting another multiplication operation to be scheduled in a next stage of the execution schedule responsive to meeting the first condition or a second condition, the second condition including having a dependency that is fulfilled by a previous stage. The process includes selecting another addition/subtraction operation to be scheduled in the next stage of the execution schedule responsive to meeting the first or second condition, and repeating the process until each operation has been scheduled in the execution schedule, where the execution schedule is configured for execution by an arithmetic logic unit.

Abstract: Provided are embodiments for a circuit comprising for performing hardware acceleration for elliptic curve cryptography (ECC). The circuit includes a code array comprising instructions for performing complex modular arithmetic; and a data array storing values corresponding to one or more complex numbers. The modular arithmetic unit includes a first multiplier and a first accumulation unit, a second multiplier and a second accumulation unit, and a third multiplier and a third accumulation unit, wherein the first, second, and third multiplier and accumulation units are cascaded and configured to perform hardware computation of complex modular operations. Also provided are embodiments of a computer program product and a method for performing the hardware acceleration of super-singular isogeny key encryption (SIKE) operations.

Abstract: A computer-implemented method includes receiving performing a fused modular multiply and add operation to compute d=((a*b)+c) % p, wherein a, b, and c, are provided as a set of operands. A first multiply-and-accumulate unit computes a binary multiplication to compute a*b. A second multiply-and-accumulate unit computes a first intermediate result by updating a result of the binary multiplication using p. An accumulator of a third multiply-and-accumulate unit is initialized with c. The third multiply-and-accumulate unit computes a second intermediate result using the first intermediate result and c. An adder unit subtracts a portion of the second intermediate result from a portion of the result of the binary multiplication. The output of the adder is provided as a result of the fused modular multiply and add operation.

Abstract: A computer-implemented method includes receiving, by a processing unit, an input-value of an operand used by a computer-executable instruction. The method further includes generating, by the processing unit, an encrypted-value by encrypting the input-value, and storing the encrypted-value in a memory. In response to a request to execute the computer-executable instruction, the processing unit decodes the computer-executable instruction into a machine-executable code and decrypts the encrypted-value for use by the machine-executable code. Upon executing the machine-executable code, the processing unit generates an encrypted-result by encrypting a result of the execution, stores the encrypted-result in the memory.

Abstract: A computer-implemented method includes receiving, by a processing unit, an instruction to perform a masked shift add operation with a set of operands. A logical AND operation is performed on a first pair of operands from the set of operands to obtain a first intermediate result. The first intermediate result is shifted by a first shift amount that is based on a first operand from the first pair of operands. A logical AND operation is performed on a second pair of operands from the set of operands to obtain a second intermediate result. The second intermediate result is shifted by a second shift amount that is based on a first operand from the second pair of operands. The shifted first intermediate result is added with the shifted second intermediate result. The method further includes outputting, as a result of the masked shift add operation, an output of the adding.

Abstract: Techniques for computing a multiplicative modular inverse of two numbers is described. In the case of a and p, p being an n-bit integer, computing the multiplicative modular inverse includes loading in a first register the value of a, and computing, using a first modular multiplier, a square of the first register n times. Concurrently, using a second modular multiplier, an is computed. Further, a product of outputs from the first modular multiplier and the second modular multiplier is computed as a result of the multiplicative modular inverse of a and p. In cases where p has more than n bits, the multiplicative modular inverse is computed iteratively using n-bit windows.

Abstract: Cryptographic-related processing is facilitated by obtaining multiple input operands, and packing the multiple input operands together to form a packed integer. The packed integer is an n-bit integer including multiple slots, where input operands of the multiple input operands are packed into every other slot of the multiple slots, and each slot of the multiple slots has a bitwidth k. Further, the process includes providing the packed integer as input to an n-bit accelerator to facilitate performing one or more predefined operations using the packed integer, to transform the packed integer into result data which facilitates cryptographic-related processing.

Abstract: Cryptographic-related processing is performed using an n-bit accelerator. The processing includes providing a binary operand to a multiply-and-accumulate unit of the n-bit accelerator. The multiply-and-accumulate unit performs an operation using the binary operand and a predetermined fractional constant F to obtain an operation result, and rounds the operation result by discarding x least-significant bits of the operation result to obtain a fractionally-scaled result, where x is a configurable number of bits to discard from the operation result, and the fractionally-scaled result facilitates performing the cryptographic-related processing.

Abstract: A method for transcoding an encoded video stream uploaded to a host server that includes a video transcoding engine connected to the server. At least one processor of the video transcoding engine receives an encoded video stream from a client computing device in which the encoded video stream is directly received by the video transcoding engine connected to the host server and the video transcoding engine has direct access to a non-volatile memory of the host server. The at least one processor of the video transcoding engine generates one or more transcoded files in real-time from the encoded video stream. The at least one processor transfers the one or more transcoded video files from the video transcoding engine directly to the non-volatile memory of the host server.

Abstract: Provided are embodiments for a circuit comprising for performing hardware acceleration for elliptic curve cryptography (ECC). The circuit includes a code array comprising instructions for performing complex modular arithmetic; and a data array storing values corresponding to one or more complex numbers. The modular arithmetic unit includes a first multiplier and a first accumulation unit, a second multiplier and a second accumulation unit, and a third multiplier and a third accumulation unit, wherein the first, second, and third multiplier and accumulation units are cascaded and configured to perform hardware computation of complex modular operations. Also provided are embodiments of a computer program product and a method for performing the hardware acceleration of super-singular isogeny key encryption (SIKE) operations.

Abstract: Aspects of the invention include physical design-optimal Dadda architectures that scale with increasing operand size. Partial product arrays can be generated for two n-bit operands and columns in the partial product arrays can be shifted to a first row. The number of partial products in each column can be iteratively reduced across one or more stages until each column has at most two partial products. At each stage a maximum column height is determined and each column having a height greater than the maximum column height is reduced using half-adders and full-adders. Result bits of the half-adders and the full-adders are placed at the bottom of the current column and carry bits of the half-adders and the full-adders are placed at the bottom of the next column.

Abstract: Embodiments are directed to elliptic curve cryptography scalar multiplications in a generic field with heavy pipelining between field operations. A bit width is determined of operands in data to be processed by a modular hardware block. It is checked whether the bit width of the operands matches a fixed bit width of the modular hardware block. In response to there being a match, the modular hardware block processes the operands. In response to there being a mismatch, the operands are modified to be accommodated by the fixed bit width of the modular hardware block.

Abstract: Embodiments are directed to selecting a multiplication operation to be scheduled in a first stage of an execution schedule, the multiplication operation meeting a first condition of having no dependency. An addition/subtraction operation is selected to be scheduled in the first stage of the execution schedule responsive to meeting the first condition. A process is performed which includes selecting another multiplication operation to be scheduled in a next stage of the execution schedule responsive to meeting the first condition or a second condition, the second condition including having a dependency that is fulfilled by a previous stage. The process includes selecting another addition/subtraction operation to be scheduled in the next stage of the execution schedule responsive to meeting the first or second condition, and repeating the process until each operation has been scheduled in the execution schedule, where the execution schedule is configured for execution by an arithmetic logic unit.