Patents by Inventor Rajat Roy

Rajat Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240161276
    Abstract: Disclosed are systems and methods for predicting response of triple-negative breast cancer to neoadjuvant chemotherapy using a deep convolutional neural network-based artificial intelligence tool a method of predicting patient response to therapy. The system divides patient tissue image slides into multiple tiles. A convolutional neural network (CNN) is trained based on the multiple tiles. The system may perform artifact detection and cancer classification to identify patterns and features that capture tumor cell heterogeneity along with stromal and tumor micro environment (TME) components of a second set of patient tissue image tiles.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 16, 2024
    Inventors: Parag Jain, Rajat Roy, Savitri Krishnamurthy, Debasish Tripathy
  • Patent number: 11972870
    Abstract: Disclosed are systems and methods for predicting patient response to a treatment option. In one embodiment, the image slides from patient tissue samples are divided into patches and morphological patterns correlated with a disease outcome are labeled and given a patch-level score, based on whether the morphological patterns occur only in patients with good outcomes or patients with poor outcomes. A patient-level score can be generated based, at least partly, on the patch-level scores. Patch-level scores can identify regions of interest for targeted biomarker identification.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: April 30, 2024
    Assignee: PATHOMIQ INC.
    Inventors: Parag Jain, Rajat Roy, Bijay Shankar Jaiswal
  • Publication number: 20230111704
    Abstract: Disclosed are systems and methods for predicting patient response to a treatment option. In one embodiment, the image slides from patient tissue samples are divided into patches and morphological patterns correlated with a disease outcome are labeled and given a patch-level score, based on whether the morphological patterns occur only in patients with good outcomes or patients with poor outcomes. A patient-level score can be generated based, at least partly, on the patch-level scores. Patch-level scores can identify regions of interest for targeted biomarker identification.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 13, 2023
    Inventors: Parag Jain, Rajat Roy, Bijay Shankar Jaiswal
  • Patent number: 11482335
    Abstract: Disclosed are systems and methods for predicting patient response to a treatment option. In one embodiment, the image slides from patient tissue samples are divided into patches and morphological patterns correlated with a disease outcome are labeled and given a patch-level score, based on whether the morphological patterns occur only in patients with good outcomes or patients with poor outcomes. A patient-level score can be generated based, at least partly, on the patch-level scores. Patch-level scores can identify regions of interest for targeted biomarker identification.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 25, 2022
    Assignee: PATHOMIQ INC.
    Inventors: Parag Jain, Rajat Roy, Bijay Shankar Jaiswal
  • Publication number: 20210249101
    Abstract: Methods and systems for identifying and quantifying molecular biomarkers and for predicting patient response to cancer therapy are provided. The disclosed methods and systems make use of artificial intelligence to capture morphometric changes from histopathology tissue that correlate with molecular changes. The system may analyze molecular markers which are predictive of tumor response and have no defined correlation with morphological features. The system may use artificial intelligence to correlate morphometric changes with critical gene modifications and molecular changes.
    Type: Application
    Filed: February 11, 2021
    Publication date: August 12, 2021
    Inventors: Parag Jain, Rajat Roy, Bijay Shankar Jaiswal
  • Publication number: 20210193323
    Abstract: Disclosed are systems and methods for predicting patient response to a treatment option. In one embodiment, the image slides from patient tissue samples are divided into patches and morphological patterns correlated with a disease outcome are labeled and given a patch-level score, based on whether the morphological patterns occur only in patients with good outcomes or patients with poor outcomes. A patient-level score can be generated based, at least partly, on the patch-level scores. Patch-level scores can identify regions of interest for targeted biomarker identification.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Parag Jain, Rajat Roy, Bijay Shankar Jaiswal
  • Patent number: 5938728
    Abstract: A network interface for a workstation, configured to be powered down to a standby mode while the network interface remains in a powered-up condition, includes a bypass circuit configured to enable configuration registers in the network interface to complete loading of configuration information in a known state, regardless of an absence of an external data clock from the network during the initialization interval. The bypass circuit ensures that the configuration registers in the network interface that require a network clock (e.g., a transmit clock or a receive clock) are maintained in a known state to enable the network interface to be independently initialized. One example of the bypass circuit holds a power on reset signal until the necessary network clock signal is detected for a predetermined number of detected clock cycles.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: August 17, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeffrey Roy Dwork, Ching Yu, Robert Alan Williams, Rajat Roy
  • Patent number: 5878028
    Abstract: A data structure to provide high performance in the transmit portion of an ethernet controller. The data structure includes the data to be transmitted, the STATUS information of the data to be transmitted, and the DESCRIPTOR information of the data to be transmitted. The data is organized in 8-bit bytes in 32-bit rows, the 32 bit STATUS information is organized in four 8-bit bytes in a 32 bit row, and the 32 bit DESCRIPTOR information is organized in four 8-bit bytes in a 32 bit row. A one-bit tag field is associated with each of the rows and a 1 in the tag field indicates that the end-of-packet is located in the row associated with that tag. The lower four bits of a STATUS byte contains information indicating which byte in the row contains the end-of-packet.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: March 2, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rajat Roy, Jeffrey Dwork, Jenny Fischer
  • Patent number: 5819113
    Abstract: A method of precisely identifying the end of packet location in a memory device. A first and second memory location in the memory device are reserved and a sequence of data is written into the memory device in sequential memory locations. When the last of the sequence of data is written into memory the memory location is written into the first reserved memory location. The second memory location is written to show that the end of packet has been written into memory.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: October 6, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alok Singh, Rajat Roy
  • Patent number: 5818844
    Abstract: An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending requests from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: October 6, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alok Singh, Rajat Roy, Jerry Kuo
  • Patent number: 5811995
    Abstract: A circuit and method for switching between different frequency clock domains that are out of phase. The circuit has a select input for selecting which frequency domain is to be output, a first circuit associated with the first clock domain, and a second circuit associated with the second clock domain. The first and second circuits are responsive to the select input and work together to disengage the first clock before the second clock is engaged.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: September 22, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rajat Roy, Jerry Kuo, Andy P. Annadurai