Patents by Inventor Rajat Sagar
Rajat Sagar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230350819Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.Type: ApplicationFiled: June 30, 2023Publication date: November 2, 2023Inventors: Niraj Nandan, Mihir Mody, Rajat Sagar
-
Patent number: 11693795Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.Type: GrantFiled: December 30, 2020Date of Patent: July 4, 2023Assignee: Texas Instruments IncorporatedInventors: Niraj Nandan, Mihir Mody, Rajat Sagar
-
Patent number: 11681598Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.Type: GrantFiled: December 28, 2020Date of Patent: June 20, 2023Assignee: Texas Instruments IncorporatedInventors: Rajat Sagar, Niraj Nandan, Kedar Chitnis, Brijesh Jadav, Mihir Mody
-
Publication number: 20230016766Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.Type: ApplicationFiled: September 15, 2022Publication date: January 19, 2023Inventors: Rajat SAGAR, Mihir Narendra MODY, Anthony Joseph LELL, Gregory Raymond SHURTZ
-
Patent number: 11447071Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.Type: GrantFiled: June 7, 2021Date of Patent: September 20, 2022Assignee: Texas Instmments IncorporatedInventors: Rajat Sagar, Mihir Narendra Mody, Anthony Joseph Lell, Gregory Raymond Shurtz
-
Patent number: 11276134Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.Type: GrantFiled: April 14, 2020Date of Patent: March 15, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mihir Narendra Mody, Niraj Nandan, Rajat Sagar, Shashank Dabral, Anthony Lell, Brijesh Jadav
-
Publication number: 20210326276Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.Type: ApplicationFiled: December 30, 2020Publication date: October 21, 2021Inventors: Niraj Nandan, Mihir Mody, Rajat Sagar
-
Publication number: 20210326229Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.Type: ApplicationFiled: December 28, 2020Publication date: October 21, 2021Inventors: Rajat Sagar, Niraj Nandan, Kedar Chitnis, Brijesh Jadav, Mihir Mody
-
Publication number: 20210291735Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Rajat SAGAR, Mihir Narendra MODY, Anthony Joseph LELL, Gregory Raymond SHURTZ
-
Publication number: 20210209719Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.Type: ApplicationFiled: April 14, 2020Publication date: July 8, 2021Inventors: Mihir Narendra MODY, Niraj NANDAN, Rajat SAGAR, Shashank DABRAL, Anthony LELL, Brijesh JADAV
-
Publication number: 20210170945Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.Type: ApplicationFiled: December 10, 2019Publication date: June 10, 2021Inventors: Rajat SAGAR, Mihir Narendra MODY, Anthony Joseph LELL, Gregory Raymond SHURTZ
-
Patent number: 11027656Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.Type: GrantFiled: December 10, 2019Date of Patent: June 8, 2021Assignee: Texas Instruments IncorporatedInventors: Rajat Sagar, Mihir Narendra Mody, Anthony Joseph Lell, Gregory Raymond Shurtz
-
Patent number: 10388392Abstract: A device is provided that includes a processor, a flash memory configured to store error correcting code (ECC) blocks for execution in place (XIP) processing by the processor, wherein an ECC block includes a data block and an ECC code for the data block, a flash interface controller coupled to the flash memory, and an error correcting code (ECC) engine coupled between the processor and the flash interface controller, wherein the ECC engine is configured to receive a read command for the flash memory from the processor, to translate a read address to an ECC block address, to read the ECC block at the ECC block address from the flash memory via the flash interface controller, and to verify the ECC code in the read ECC block.Type: GrantFiled: April 8, 2017Date of Patent: August 20, 2019Assignee: Texas Instruments IncorporatedInventors: Peter Aberl, Aishwarya Dubey, Rajat Sagar, Eldad Falik
-
Patent number: 10380746Abstract: An optical flow system includes a binary mask generation circuit and an optical flow circuit. The binary mask generation circuit is configured to receive a plurality of points of interest from a captured image that contains an array of pixels arranged as rows and columns and includes width lines that correspond to the rows and height lines that correspond to the columns. The binary mask generation circuit is also configured to generate a binary mask based on the plurality of points of interest. The binary mask includes a representation of a subset of the plurality of points of interest. The optical flow circuit is configured to receive the binary mask and generate an optical flow map of the subset of the plurality of points of interest.Type: GrantFiled: October 16, 2017Date of Patent: August 13, 2019Assignee: Texas Instruments IncorporatedInventors: Hetul Sanghvi, Mihir Narendra Mody, Mike Lachmayr, Anish Reghunath, Rajat Sagar
-
Publication number: 20190114786Abstract: An optical flow system includes a binary mask generation circuit and an optical flow circuit. The binary mask generation circuit is configured to receive a plurality of points of interest from a captured image that contains an array of pixels arranged as rows and columns and includes width lines that correspond to the rows and height lines that correspond to the columns. The binary mask generation circuit is also configured to generate a binary mask based on the plurality of points of interest. The binary mask includes a representation of a subset of the plurality of points of interest. The optical flow circuit is configured to receive the binary mask and generate an optical flow map of the subset of the plurality of points of interest.Type: ApplicationFiled: October 16, 2017Publication date: April 18, 2019Inventors: Hetul SANGHVI, Mihir Narendra MODY, Mike LACHMAYR, Anish REGHUNATH, Rajat SAGAR
-
Publication number: 20180293129Abstract: A device is provided that includes a processor, a flash memory configured to store error correcting code (ECC) blocks for execution in place (XIP) processing by the processor, wherein an ECC block includes a data block and an ECC code for the data block, a flash interface controller coupled to the flash memory, and an error correcting code (ECC) engine coupled between the processor and the flash interface controller, wherein the ECC engine is configured to receive a read command for the flash memory from the processor, to translate a read address to an ECC block address, to read the ECC block at the ECC block address from the flash memory via the flash interface controller, and to verify the ECC code in the read ECC block.Type: ApplicationFiled: April 8, 2017Publication date: October 11, 2018Inventors: Peter Aberl, Aishwarya Dubey, Rajat Sagar, Eldad Falik
-
Patent number: 9628787Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.Type: GrantFiled: January 27, 2015Date of Patent: April 18, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rahul Gulati, Vasant Easwaran, Mihir Narendra Mody, Prashant Dinkar Karandikar, Prithvi Y. A. Shankar, Aishwarya Dubey, Kedar Chitnis, Rajat Sagar
-
Patent number: 9525865Abstract: A method of analyzing a digital camera includes generating first image data using an image sensor in the camera. A first analysis is performed on at least one portion of the first image data. Second image data is generated using the image sensor and a second analysis is performed on the at least one portion of the second image data. The results of the first analysis are compared to the results of the second analysis. A signal indicating a fault with the digital camera is generated in response to the first analysis differing from the second analysis by a predetermined amount.Type: GrantFiled: October 23, 2014Date of Patent: December 20, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Rajat Sagar
-
Publication number: 20160119617Abstract: A method of analyzing a digital camera includes generating first image data using an image sensor in the camera. A first analysis is performed on at least one portion of the first image data. Second image data is generated using the image sensor and a second analysis is performed on the at least one portion of the second image data. The results of the first analysis are compared to the results of the second analysis. A signal indicating a fault with the digital camera is generated in response to the first analysis differing from the second analysis by a predetermined amount.Type: ApplicationFiled: October 23, 2014Publication date: April 28, 2016Inventor: Rajat Sagar
-
Publication number: 20150304648Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.Type: ApplicationFiled: January 27, 2015Publication date: October 22, 2015Inventors: Rahul Gulati, Vasant Easwaran, Mihir Narendra Mody, Prashant Dinkar Karandikar, Prithvi Y.A. Shankar, Aishwarya Dubey, Kedar Chitnis, Rajat Sagar