Abstract: Techniques are disclosed involving operand management using a fusion buffer. A processor includes operand management circuitry, where the operand management circuitry includes a fusion buffer, and execution circuitry. In one embodiment, the operand management circuitry is configured to detect a first storage instruction operation that is executable to store operand values usable by one or more consumer instruction operations and store the first storage instruction operation in the fusion buffer. In response to detecting a drop condition associated with the first storage instruction operation, the operand management circuitry is configured to remove the first storage instruction operation from the fusion buffer without forwarding the first storage instruction operation for execution. In response to detecting a buffer vacate condition and not detecting the drop condition the operand management circuitry is configured to forward the first storage instruction operation for execution by the execution circuitry.

Abstract: Techniques are disclosed involving operand management using a fusion buffer. A processor includes operand management circuitry, where the operand management circuitry includes a fusion buffer, and execution circuitry. In one embodiment, the operand management circuitry is configured to detect a first storage instruction operation that is executable to store operand values usable by one or more consumer instruction operations and store the first storage instruction operation in the fusion buffer. In response to detecting a drop condition associated with the first storage instruction operation, the operand management circuitry is configured to remove the first storage instruction operation from the fusion buffer without forwarding the first storage instruction operation for execution. In response to detecting a buffer vacate condition and not detecting the drop condition the operand management circuitry is configured to forward the first storage instruction operation for execution by the execution circuitry.

Abstract: Techniques are disclosed involving interleaving and de-interleaving of operands. An embodiment of an apparatus includes an array storage circuit and a control circuit. The array storage circuit is configured to store elements of an array having a plurality of rows and a plurality of columns. The control circuit is configured to write multiple input vectors to the array storage circuit such that elements of a given input vector are split among multiple columns of the plurality of columns and a given row of the plurality of rows has interleaved elements of the multiple input vectors. The control circuit is further configured to output data corresponding to rows of the array to form one or more result values.

Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.

Abstract: An instruction set architecture including instructions for a processor and instructions for a coprocessor may include synchronizing instructions that may be used to begin and end instruction sequences that include coprocessor instructions (coprocessor sequences). If a terminating synchronizing instruction is followed by an initial synchronizing instruction and the pair are detected in the coprocessor concurrently, the coprocessor may suppress execution of the pair of instructions.

Abstract: An instruction set architecture including instructions for a processor and instructions for a coprocessor may include synchronizing instructions that may be used to begin and end instruction sequences that include coprocessor instructions (coprocessor sequences). If a terminating synchronizing instruction is followed by an initial synchronizing instruction and the pair are detected in the coprocessor concurrently, the coprocessor may suppress execution of the pair of instructions.

Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.

Abstract: An instruction set architecture including instructions for a processor and instructions for a coprocessor may include synchronizing instructions that may be used to begin and end instruction sequences that include coprocessor instructions (coprocessor sequences). If a terminating synchronizing instruction is followed by an initial synchronizing instruction and the pair are detected in the coprocessor concurrently, the coprocessor may suppress execution of the pair of instructions.

Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.