Patents by Inventor Rajeev A. Jain

Rajeev A. Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240022451
    Abstract: In an example, a network switch is to receive a loop detect packet from an access netwssork connected to a Data center network (DCN). The DCN includes a VXLAN overlay and the network switch is configured as a VTEP. The network switch compares the VNI of a source VTEP from which the loop detect packet originates with a locally configured VNI. In response to a match, it is determined that the network switch is configured as a peer VTEP. Import RT in the loop detect packet is compared with an export RT of the peer VTEP and the export RT in the loop detect packet is compared with an import RT of the peer VTEP. Based on the comparison, it is determined whether a VXLAN tunnel is configured between the peer and the source VTEPs. In response to the VXLAN tunnel being configured, the switch may determine that a network loop is present.
    Type: Application
    Filed: July 18, 2022
    Publication date: January 18, 2024
    Inventors: Saumya Dikshit, Rajeev Jain
  • Publication number: 20230125208
    Abstract: Disclosed herein are pharmaceutical compositions having a mixture of at least one active agent and an ion exchange resin, such that the composition releases about 75% or more of the at least one active agent within about 1 hour as measured by in-vitro dissolution in a USP Apparatus 2 (paddle) at about 50 rpm in about 900 ml 0.1N HCl at about 37° C. and related methods. Also disclosed herein are pharmaceutical compositions having a mixture of a drug susceptible to abuse, a non-opioid analgesic and an ion exchange resin, the composition further including at least one gelling agent and related methods.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 27, 2023
    Inventors: Gerard P. Frunzi, Sibao Chen, Rajeev A. Jain
  • Patent number: 11564918
    Abstract: Disclosed herein are pharmaceutical compositions having a mixture of at least one active agent and an ion exchange resin, such that the composition releases about 75% or more of the at least one active agent within about 1 hour as measured by in-vitro dissolution in a USP Apparatus 2 (paddle) at about 50 rpm in about 900 ml 0.1N HCl at about 37° C. and related methods. Also disclosed herein are pharmaceutical compositions having a mixture of a drug susceptible to abuse, a non-opioid analgesic and an ion exchange resin, the composition further including at least one gelling agent and related methods.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: January 31, 2023
    Assignee: RHODES PHARMACEUTICALS L.P.
    Inventors: Gerard P. Frunzi, Sibao Chen, Rajeev A. Jain
  • Publication number: 20220239979
    Abstract: Systems, methods, and non-transitory computer-readable media can receive information describing one or more viewed media content items from a plurality of computing devices. Each computing device can communicate with the computing system over a persistent network connection. The information describing the one or more viewed media content items received from the plurality of computing devices can be aggregated. The aggregated information can be used to re-rank a set of media content items for one or more users.
    Type: Application
    Filed: October 26, 2018
    Publication date: July 28, 2022
    Inventors: Abhinav Rajeev Jain, Cam Thach Nguyen, Felix Leupold, Bjoern Alexander Lin Ryden Blom
  • Patent number: 11157066
    Abstract: A floorplan independent and cross-current free distributed adaptive power multiplexer (APM) is disclosed. In some implementations, an APM includes a first switch path coupled between a first voltage supply rail and an output terminal, the first switch path including a first switch; a second switch path coupled between a second voltage supply rail and the output terminal, the second switch path including a second switch, wherein the first switch and the second switch are configured to select one of a first voltage supply and a second voltage supply as an output voltage supply to be output at the voltage output terminal; and a comparator coupled to the first and the second voltage supply rails, and the voltage output terminal, wherein the comparator is configured to compare the output voltage supply with one of the first and the second voltage supplies and to output a control signal.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: October 26, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Byron Murphy, Rajeev Jain, Lipeng Cao, Harshat Pant
  • Publication number: 20210306252
    Abstract: Examples disclosed herein relate to a method comprising receiving a control packet originating from a originating network device. The control packet may have a control MAC address identifying the originating network device and the control packet is used for determining a traffic loop in a network including the first network device and the originating network device. The method may include determining, by the first network device, whether the control MAC address of the control packet matches a MAC address of the first network device. Wit is determined that the control MAC address of the control packet matches a MAC address of the first network device, the method may include determining that the match is indicative of the loop and blocking a port of the first network device that the control packet arrived on without blocking any other ports on the first network device.
    Type: Application
    Filed: February 25, 2021
    Publication date: September 30, 2021
    Inventors: Rajeev Jain, Ayush Shukla
  • Patent number: 11047946
    Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 29, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Nam Dang, Rajeev Jain, Swarna Navubothu, Alan Lewis, Martin Saint-Laurent, Tung Nang Pham, Joseph Terregrossa, Paras Gupta, Somasekhar Maradani
  • Publication number: 20210159906
    Abstract: A multilevel analog to digital converter (ADC) is composed of noise shaping filter and multi-level quantizer, where said quantizer is made from an array of comparators, each coupled with one reference level, the said quantizer is coupled with a thermometric digital to analog converters (DAC) in the feedback path, the said DAC output is compared with ADC input and error is fed to noise shaping filter, said reference levels of each quantizer is generated from a digital to analog converter coupled with a digital quantizer reference controller and said digital quantizer reference controller is randomly changing the reference levels in a way that quantizer coupled DAC elements are indirectly randomised to improve the overall linearity and noise performance of the converter.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 27, 2021
    Applicant: VERVESEMI MICROELECTRONICS PRIVATE LIMITED
    Inventors: Pratap Narayan SINGH, Rajeev JAIN, Ashish Kumar SHARMA, Chinmaya DASH
  • Patent number: 10734985
    Abstract: In certain aspects, a comparator includes a first inverter having an input, an output, and a voltage supply input, wherein the input of the first inverter and the output of the first inverter are coupled together, and the voltage supply input of the first inverter is configured to receive a first compare voltage. The comparator also includes a second inverter having an input, an output, and a voltage supply input, wherein the input of the second inverter is coupled to the output of the first inverter, and the voltage supply input of the second inverter is configured to receive a second compare voltage.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Byron Murphy, Glenn Murphy, Rajeev Jain
  • Patent number: 10712807
    Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Harshat Pant, Rajeev Jain, Byron Glenn Murphy, Lipeng Cao
  • Publication number: 20200192461
    Abstract: A floorplan independent and cross-current free distributed adaptive power multiplexer (APM) is disclosed. In some implementations, an APM includes a first switch path coupled between a first voltage supply rail and an output terminal, the first switch path including a first switch; a second switch path coupled between a second voltage supply rail and the output terminal, the second switch path including a second switch, wherein the first switch and the second switch are configured to select one of a first voltage supply and a second voltage supply as an output voltage supply to be output at the voltage output terminal; and a comparator coupled to the first and the second voltage supply rails, and the voltage output terminal, wherein the comparator is configured to compare the output voltage supply with one of the first and the second voltage supplies and to output a control signal.
    Type: Application
    Filed: November 21, 2019
    Publication date: June 18, 2020
    Inventors: Byron MURPHY, Rajeev JAIN, Lipeng CAO, Harshat PANT
  • Publication number: 20200195241
    Abstract: In certain aspects, a comparator includes a first inverter having an input, an output, and a voltage supply input, wherein the input of the first inverter and the output of the first inverter are coupled together, and the voltage supply input of the first inverter is configured to receive a first compare voltage. The comparator also includes a second inverter having an input, an output, and a voltage supply input, wherein the input of the second inverter is coupled to the output of the first inverter, and the voltage supply input of the second inverter is configured to receive a second compare voltage.
    Type: Application
    Filed: April 4, 2019
    Publication date: June 18, 2020
    Inventors: Byron MURPHY, Glenn MURPHY, Rajeev JAIN
  • Publication number: 20190391608
    Abstract: A power multiplexer system including a power mux controller, wherein the power mux controller generates at least one non-regulated control signal; a regulator coupled to the power mux controller, wherein the regulator generates a reference voltage and wherein the reference voltage is used for generating a regulated control signal; and at least one power multiplexer tile coupled to the regulator, wherein each of the at least one power multiplexer tile includes a first branch comprising a first plurality of transistors and a second branch comprising a second plurality of transistors, and wherein enabling or disabling one or more of the first plurality of transistors is based on either the at least one non-regulated control signal or the regulated control signal.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: Lipeng CAO, Rajeev JAIN, Harshat PANT, Byron Glenn MURPHY
  • Publication number: 20190346528
    Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Inventors: Nam DANG, Rajeev JAIN, Swarna NAVUBOTHU, Alan LEWIS, Martin SAINT-LAURENT, Tung Nang PHAM, Joseph TERREGROSSA, Paras GUPTA, Somasekhar MARADANI
  • Publication number: 20190302876
    Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Harshat Pant, Rajeev Jain, Byron Glenn Murphy, Lipeng Cao
  • Publication number: 20190262334
    Abstract: Disclosed herein are pharmaceutical compositions having a mixture of at least one active agent and an ion exchange resin, such that the composition releases about 75% or more of the at least one active agent within about 1 hour as measured by in-vitro dissolution in a USP Apparatus 2 (paddle) at about 50 rpm in about 900 ml 0.1N HCl at about 37° C. and related methods. Also disclosed herein are pharmaceutical compositions having a mixture of a drug susceptible to abuse, a non-opioid analgesic and an ion exchange resin, the composition further including at least one gelling agent and related methods.
    Type: Application
    Filed: October 10, 2017
    Publication date: August 29, 2019
    Inventors: Gerard P. Frunzi, Sibao Chen, Rajeev A. Jain
  • Patent number: 10317968
    Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: June 11, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Harshat Pant, Rajeev Jain, Sassan Shahrokhinia, Lam Ho
  • Publication number: 20180284859
    Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Inventors: Harshat Pant, Rajeev Jain, Sassan Shahrokhinia, Lam Ho
  • Patent number: 9990022
    Abstract: An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 5, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Mong Chit Wong, Nam Dang, Rajeev Jain, Sassan Shahrokhinia, Yu Huang, Lipeng Cao
  • Publication number: 20180004276
    Abstract: An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Mong Chit Wong, Nam Dang, Rajeev Jain, Sassan Shahrokhinia, Yu Huang, Lipeng Cao