Abstract: Methods, systems, and computer readable media for generating SDN policies are disclosed. One system includes a processor and a memory. The system also includes an SDN policy synthesizer (SPS) implemented using the processor and the memory. The SPS is configured to receive scenario based information indicating one or more behaviors for at least one SDN policy, to use a synthesis algorithm for generating the at least one SDN policy based on the scenario based information, and to provide the at least one SDN policy to an SDN controller.

Abstract: Methods, systems, and computer readable media for generating SDN policies are disclosed. One system includes a processor and a memory. The system also includes an SDN policy synthesizer (SPS) implemented using the processor and the memory. The SPS is configured to receive scenario based information indicating one or more behaviors for at least one SDN policy, to use a synthesis algorithm for generating the at least one SDN policy based on the scenario based information, and to provide the at least one SDN policy to an SDN controller.

Abstract: A system and method for determining whether a set of message sequence charts (MSCs) is realizable or safely realizable in an implementation is provided. The determination is made by analyzing the set of MSCs for the existence of unspecified, implied MSCs. If the set of MSCs can be realized in a deadlock-free automaton, then the set of MSCs is safely realizable. If the set of MSCs is realizable (no implied MSCs exist), a state machine can be synthesized from the set of MSCs. If the set of MSCs is not realizable, then implied, unspecified (partial) MSCs are produced. Also, given an undesirable MSC, the system determines whether the set of required MSCs implies the given undesired MSC.

Abstract: Model checking for message sequence charts (MSCs), message sequence chart graphs and hierarchical message sequence chart graphs (HMSCs) is provided. To verify the behavior of a given MSC, MSC graph and HMSC, a specification automaton is constructed. This specification automaton specifies the undesirable executions of the model under analysis. From the model under analysis, linearizations are defined from the model and a finite test automaton is constructed from the linearizations. The test automaton and the specification automaton are combined and it is determined whether there is an execution in the intersection. Where no state in the specification automaton is reachable from the test automaton, the model is verified.

Abstract: Model checking is applied to a hierarchical state machine (i.e., a state machine having at least one state (i.e., a superstate) that is itself a state machine) without first flattening the hierarchical state machine. In one embodiment, the model checking involves one or more or reachability, cycle-detection, linear-time requirements, and branching-time requirements analyses. For reachability analysis, in addition to keeping track of whether states have been visited, the algorithm also keeps track of the exit nodes for each superstate. Cycle-detection analysis has two phases: a primary phase in which target states are identified and a secondary phase in which it is determined whether identified target states are part of closed processing paths or loops. For cycle-detection analysis, the algorithm keeps track of (1) whether states have been visited during the primary phase, (2) the exit nodes for each superstate, and (3) whether states have been visited during the secondary phase.

Abstract: Apparatus for developing and verifying systems. The disclosed apparatus employs a computationally-tractable technique for verifying whether a system made up of a set of processes, each of which has at least one delay constraint associated with it, satisfies a given temporal property. The technique deals with the verification as a language inclusion problem, i.e., it represents both the set of processes and the temporal property as automata and determines whether there is a restriction of the set of processes such that the language of the automaton representing the restricted set of processes is included in the language of the automaton representing the temporal property.