Patents by Inventor Rajeev CHANDWANI

Rajeev CHANDWANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10171358
    Abstract: Systems and methods for port congestion resiliency in a Link Aggregation Group (LAG) including a multi-card LAG and/or a multi-switch LAG. A method includes receiving a packet for egress over the LAG; responsive to determining no congestion over internal ports not part of the LAG, hashing with all member ports in the LAG in a distribution state; and, responsive to determining congestion over the internal ports, hashing with only member ports on a local card in which the packet was received, wherein the hashing determines which member port the packet egresses from in the LAG. The multi-card LAG includes multiple cards where packets ingress and egress from, and the cards communicate via a backplane port which is not part of the LAG. The multi-switch LAG includes multiple chassis where packets ingress and egress from, and the chassis communicate via an inter-switch connectivity port which is not part of the LAG.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: January 1, 2019
    Assignee: Ciena Corporation
    Inventors: Anubhav Saksena, Rajeev Chandwani, Shivam Agarwal
  • Publication number: 20170230294
    Abstract: Systems and methods for port congestion resiliency in a Link Aggregation Group (LAG) including a multi-card LAG and/or a multi-switch LAG. A method includes receiving a packet for egress over the LAG; responsive to determining no congestion over internal ports not part of the LAG, hashing with all member ports in the LAG in a distribution state; and, responsive to determining congestion over the internal ports, hashing with only member ports on a local card in which the packet was received, wherein the hashing determines which member port the packet egresses from in the LAG. The multi-card LAG includes multiple cards where packets ingress and egress from, and the cards communicate via a backplane port which is not part of the LAG. The multi-switch LAG includes multiple chassis where packets ingress and egress from, and the chassis communicate via an inter-switch connectivity port which is not part of the LAG.
    Type: Application
    Filed: March 17, 2016
    Publication date: August 10, 2017
    Inventors: Anubhav SAKSENA, Rajeev CHANDWANI, Shivam AGARWAL