Patents by Inventor Rajeev D. Joshi
Rajeev D. Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11257739Abstract: A method includes forming a first magnetic material on a first surface of a conductive loop, forming a second magnetic material on a second surface of the conductive loop opposite the first surface to form an inductor, attaching a semiconductor die to a leadframe, and attaching the inductor to the leadframe with solder balls. The semiconductor die is between the inductor and the leadframe. The conductive loop: spans parallel to the leadframe; or is between the first magnetic material and the second magnetic material.Type: GrantFiled: July 13, 2020Date of Patent: February 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joyce Marie Mullenix, Roberto Giampiero Massolini, Rajeev D. Joshi
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Publication number: 20200343164Abstract: A method includes forming a first magnetic material on a first surface of a conductive loop, forming a second magnetic material on a second surface of the conductive loop opposite the first surface to form an inductor, attaching a semiconductor die to a leadframe, and attaching the inductor to the leadframe with solder balls. The semiconductor die is between the inductor and the leadframe. The conductive loop: spans parallel to the leadframe; or is between the first magnetic material and the second magnetic material.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventors: Joyce Marie Mullenix, Roberto Giampiero Massolini, Rajeev D. Joshi
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Patent number: 10714412Abstract: A semiconductor package includes a leadframe comprising input/output pins accessible external to the semiconductor package and a semiconductor die electrically connected to the leadframe. The semiconductor package also includes a passive electrical component mounted on a side of the semiconductor die opposite the leadframe. Mold compound encapsulates the passive electrical component, semiconductor die, and leadframe to form the semiconductor package. Associated methods are disclosed as well.Type: GrantFiled: November 22, 2017Date of Patent: July 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joyce Marie Mullenix, Roberto Giampiero Massolini, Rajeev D. Joshi
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Patent number: 10573582Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.Type: GrantFiled: April 8, 2019Date of Patent: February 25, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajeev D. Joshi, Hau Nguyen, Anindya Poddar, Ken Pham
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Publication number: 20190237395Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.Type: ApplicationFiled: April 8, 2019Publication date: August 1, 2019Inventors: Rajeev D. Joshi, Hau Nguyen, Anindya Poddar, Ken Pham
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Patent number: 10312184Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.Type: GrantFiled: November 4, 2015Date of Patent: June 4, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajeev D. Joshi, Hau Nguyen, Anindya Poddar, Ken Pham
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Publication number: 20190157188Abstract: A semiconductor package includes a leadframe comprising input/output pins accessible external to the semiconductor package and a semiconductor die electrically connected to the leadframe. The semiconductor package also includes a passive electrical component mounted on a side of the semiconductor die opposite the leadframe. Mold compound encapsulates the passive electrical component, semiconductor die, and leadframe to form the semiconductor package. Associated methods are disclosed as well.Type: ApplicationFiled: November 22, 2017Publication date: May 23, 2019Inventors: Joyce Marie MULLENIX, Roberto Giampiero MASSOLINI, Rajeev D. JOSHI
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Publication number: 20170125324Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.Type: ApplicationFiled: November 4, 2015Publication date: May 4, 2017Inventors: Rajeev D. Joshi, Hau Nguyen, Anindya Poddar, Ken Pham
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Patent number: 8278742Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.Type: GrantFiled: February 2, 2011Date of Patent: October 2, 2012Assignee: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Rajeev D. Joshi
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Patent number: 7968982Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.Type: GrantFiled: July 10, 2008Date of Patent: June 28, 2011Assignee: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Rajeev D. Joshi
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Publication number: 20110124158Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.Type: ApplicationFiled: February 2, 2011Publication date: May 26, 2011Applicant: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Rajeev D. Joshi
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Patent number: 7842555Abstract: An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.Type: GrantFiled: January 6, 2009Date of Patent: November 30, 2010Assignee: Fairchild Semiconductor CorporationInventors: Rajeev D. Joshi, Jonathan A. Noquil, Consuelo N. Tangpuz
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Publication number: 20090117690Abstract: An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.Type: ApplicationFiled: January 6, 2009Publication date: May 7, 2009Inventors: Rajeev D. Joshi, Jonathan A. Noquil, Consuelo N. Tangpuz
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Publication number: 20090072362Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.Type: ApplicationFiled: July 10, 2008Publication date: March 19, 2009Applicant: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Rajeev D. Joshi
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Patent number: 7501702Abstract: An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.Type: GrantFiled: June 24, 2004Date of Patent: March 10, 2009Assignee: Fairchild Semiconductor CorporationInventors: Rajeev D. Joshi, Jonathan A. Noquil, Consuelo N. Tangpuz
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Patent number: 7468548Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.Type: GrantFiled: December 9, 2005Date of Patent: December 23, 2008Assignee: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Rajeev D. Joshi