Patents by Inventor Rajeev D. Muralidhar
Rajeev D. Muralidhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768533Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: August 2, 2022Date of Patent: September 26, 2023Assignee: Tahoe Research, Ltd.Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20230004209Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: August 2, 2022Publication date: January 5, 2023Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 11422615Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: January 13, 2020Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10768680Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.Type: GrantFiled: August 15, 2017Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
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Publication number: 20200272219Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: January 13, 2020Publication date: August 27, 2020Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10671404Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.Type: GrantFiled: February 14, 2018Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri
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Patent number: 10564705Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: May 18, 2018Date of Patent: February 18, 2020Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10551900Abstract: A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.Type: GrantFiled: March 28, 2017Date of Patent: February 4, 2020Assignee: Intel CorporationInventors: Vijayakumar A. Dibbad, Satish Prathaban, Harinarayanan Seshadri, Rajeev D. Muralidhar
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Patent number: 10275853Abstract: The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.Type: GrantFiled: April 15, 2015Date of Patent: April 30, 2019Assignee: Intel CorporationInventors: Ramanathan Sethuraman, Arojit Roychowdhury, Ajaya V. Durg, Rajeev D. Muralidhar
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Publication number: 20180364792Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: May 18, 2018Publication date: December 20, 2018Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10133336Abstract: Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination.Type: GrantFiled: November 27, 2012Date of Patent: November 20, 2018Assignee: Intel CorporationInventors: Ren Wang, Tsung-Yuan C. Tai, Jr-Shian Tsai, Bruce L. Fleming, Rajeev D. Muralidhar, Mesut A. Ergin, Prakash N. Iyer, Harinarayanan Seshadri
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Publication number: 20180284863Abstract: A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.Type: ApplicationFiled: March 28, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Vijayakumar A. Dibbad, Satish Prathaban, Harinarayanan Seshadri, Rajeev D. Muralidhar
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Patent number: 10007323Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: December 23, 2013Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20180173296Abstract: An apparatus is provided which comprises: a processing core; and circuitry to select, for a first mode of operation of the processing core, a first operating point comprising a first operating frequency and a first operating load, based at least in part on a mathematical function that substantially defines variation of a frequency and a load of the processing core for a threshold power consumption, wherein the circuitry is to select the first operating point such that a first power consumption of the processing core at the first operating point is less than or equal to the threshold power consumption.Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Inventors: Noor U. Mubeen, Harinarayanan Seshadri, Rajeev D. Muralidhar, Mahesh Kumar P, Bharath K. Veera
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Publication number: 20180173538Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.Type: ApplicationFiled: February 14, 2018Publication date: June 21, 2018Applicant: INTEL CORPORATIONInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri
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Patent number: 9934048Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.Type: GrantFiled: March 29, 2016Date of Patent: April 3, 2018Assignee: INTEL CORPORATIONInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri
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Publication number: 20180059766Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.Type: ApplicationFiled: August 15, 2017Publication date: March 1, 2018Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
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Patent number: 9829963Abstract: Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform.Type: GrantFiled: December 26, 2014Date of Patent: November 28, 2017Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nithish Mahalingam, Rushikesh S. Kadam, Vishwesh M. Rudramuni, Sujith Thomas
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Publication number: 20170286125Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Applicant: INTEL CORPORATIONInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri
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Patent number: 9733689Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.Type: GrantFiled: June 27, 2015Date of Patent: August 15, 2017Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala