Abstract: A network device that can trace the path of a network loop is provided. During operation, the network device can receive a probe packet from an originating network device (OND) via an ingress port of the network device. Here, the probe packet can include a source address of the OND. The network device can determine whether the network device is the OND by comparing the source address with a local address. Upon determining that the network device is not the OND, the network device can append the local address in a payload of the probe packet and forward the probe packet via an egress port based on the destination address. On the other hand, upon determining that the network device is the OND, the network device can determine presence of a loop associated with the network device and determine a trace path of the loop based on the payload.

Abstract: A switch in a first network is provided. During operation, the switch can learn a media access control (MAC) address of a packet from a second network via a first port. The MAC address can be learned in association with an aggregate virtual local area network (VLAN) configured on the first network for traffic from the second network. The switch can inspect the packet to determine an external VLAN configured on the second network. The switch can send, via the first port a packet on the external VLAN. The source and detector addresses can be a local address. The destination address can be a multi-destination address. The switch can identify the local address as the detector address in a packet received from a second port coupling the second network, identify a loop in the second network in association with the external VLAN, and disable transmission via the second port.

Abstract: In an example, a network switch is to receive a loop detect packet from an access netwssork connected to a Data center network (DCN). The DCN includes a VXLAN overlay and the network switch is configured as a VTEP. The network switch compares the VNI of a source VTEP from which the loop detect packet originates with a locally configured VNI. In response to a match, it is determined that the network switch is configured as a peer VTEP. Import RT in the loop detect packet is compared with an export RT of the peer VTEP and the export RT in the loop detect packet is compared with an import RT of the peer VTEP. Based on the comparison, it is determined whether a VXLAN tunnel is configured between the peer and the source VTEPs. In response to the VXLAN tunnel being configured, the switch may determine that a network loop is present.

Abstract: A system for facilitating loop-free traffic forwarding is provided. During operation, the system can operate a switch as a tunnel endpoint for a plurality of tunnels with corresponding remote endpoints. The system can determine a tunnel network identifier (TNI) associated with a respective virtual local area network (VLAN) configured at the switch. The system can then enable the TNI for a first tunnel among the plurality of tunnels for carrying traffic of the VLAN. Here, traffic of the VLAN is only forwarded over the first tunnel. Therefore, the system can prevent the rest of the plurality of tunnels from looping the traffic of the VLAN back to the switch. The system can select a second tunnel as a standby tunnel for the TNI from the rest of the plurality of tunnels. If the first tunnel is unavailable, the system can enable the TNI for the second tunnel for traffic forwarding.

Abstract: In an example, a network switch is to receive a loop detect packet from an access netwssork connected to a Data center network (DCN). The DCN includes a VXLAN overlay and the network switch is configured as a VTEP. The network switch compares the VNI of a source VTEP from which the loop detect packet originates with a locally configured VNI. In response to a match, it is determined that the network switch is configured as a peer VTEP. Import RT in the loop detect packet is compared with an export RT of the peer VTEP and the export RT in the loop detect packet is compared with an import RT of the peer VTEP. Based on the comparison, it is determined whether a VXLAN tunnel is configured between the peer and the source VTEPs. In response to the VXLAN tunnel being configured, the switch may determine that a network loop is present.

Abstract: Systems, methods, and non-transitory computer-readable media can receive information describing one or more viewed media content items from a plurality of computing devices. Each computing device can communicate with the computing system over a persistent network connection. The information describing the one or more viewed media content items received from the plurality of computing devices can be aggregated. The aggregated information can be used to re-rank a set of media content items for one or more users.

Abstract: A floorplan independent and cross-current free distributed adaptive power multiplexer (APM) is disclosed. In some implementations, an APM includes a first switch path coupled between a first voltage supply rail and an output terminal, the first switch path including a first switch; a second switch path coupled between a second voltage supply rail and the output terminal, the second switch path including a second switch, wherein the first switch and the second switch are configured to select one of a first voltage supply and a second voltage supply as an output voltage supply to be output at the voltage output terminal; and a comparator coupled to the first and the second voltage supply rails, and the voltage output terminal, wherein the comparator is configured to compare the output voltage supply with one of the first and the second voltage supplies and to output a control signal.

Abstract: Examples disclosed herein relate to a method comprising receiving a control packet originating from a originating network device. The control packet may have a control MAC address identifying the originating network device and the control packet is used for determining a traffic loop in a network including the first network device and the originating network device. The method may include determining, by the first network device, whether the control MAC address of the control packet matches a MAC address of the first network device. Wit is determined that the control MAC address of the control packet matches a MAC address of the first network device, the method may include determining that the match is indicative of the loop and blocking a port of the first network device that the control packet arrived on without blocking any other ports on the first network device.

Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.

Abstract: A multilevel analog to digital converter (ADC) is composed of noise shaping filter and multi-level quantizer, where said quantizer is made from an array of comparators, each coupled with one reference level, the said quantizer is coupled with a thermometric digital to analog converters (DAC) in the feedback path, the said DAC output is compared with ADC input and error is fed to noise shaping filter, said reference levels of each quantizer is generated from a digital to analog converter coupled with a digital quantizer reference controller and said digital quantizer reference controller is randomly changing the reference levels in a way that quantizer coupled DAC elements are indirectly randomised to improve the overall linearity and noise performance of the converter.

Abstract: In certain aspects, a comparator includes a first inverter having an input, an output, and a voltage supply input, wherein the input of the first inverter and the output of the first inverter are coupled together, and the voltage supply input of the first inverter is configured to receive a first compare voltage. The comparator also includes a second inverter having an input, an output, and a voltage supply input, wherein the input of the second inverter is coupled to the output of the first inverter, and the voltage supply input of the second inverter is configured to receive a second compare voltage.

Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.

Abstract: In certain aspects, a comparator includes a first inverter having an input, an output, and a voltage supply input, wherein the input of the first inverter and the output of the first inverter are coupled together, and the voltage supply input of the first inverter is configured to receive a first compare voltage. The comparator also includes a second inverter having an input, an output, and a voltage supply input, wherein the input of the second inverter is coupled to the output of the first inverter, and the voltage supply input of the second inverter is configured to receive a second compare voltage.

Abstract: A floorplan independent and cross-current free distributed adaptive power multiplexer (APM) is disclosed. In some implementations, an APM includes a first switch path coupled between a first voltage supply rail and an output terminal, the first switch path including a first switch; a second switch path coupled between a second voltage supply rail and the output terminal, the second switch path including a second switch, wherein the first switch and the second switch are configured to select one of a first voltage supply and a second voltage supply as an output voltage supply to be output at the voltage output terminal; and a comparator coupled to the first and the second voltage supply rails, and the voltage output terminal, wherein the comparator is configured to compare the output voltage supply with one of the first and the second voltage supplies and to output a control signal.

Abstract: A power multiplexer system including a power mux controller, wherein the power mux controller generates at least one non-regulated control signal; a regulator coupled to the power mux controller, wherein the regulator generates a reference voltage and wherein the reference voltage is used for generating a regulated control signal; and at least one power multiplexer tile coupled to the regulator, wherein each of the at least one power multiplexer tile includes a first branch comprising a first plurality of transistors and a second branch comprising a second plurality of transistors, and wherein enabling or disabling one or more of the first plurality of transistors is based on either the at least one non-regulated control signal or the regulated control signal.

Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.

Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.

Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

Abstract: An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.