Abstract: Apparatuses, systems, and methods to move end connectors. In at least one embodiment, a linkage system to move an end connector between at least a first position and a second position is driven by an actuator in a first direction to drive movement of the end connector in a second direction, perpendicular to the first direction.

Abstract: A technique is disclosed for a graphics processing unit (GPU) to enter and exit a power saving deep sleep mode. The technique involves preserving processing state within local memory by configuring the local memory to operate in a self-refresh mode while the GPU is powered off for deep sleep. An interface circuit coupled to the local memory is configured to prevent spurious GPU signals from disrupting proper self-refresh of the local memory. Spurious GPU signals may result from GPU power down and GPU power up events associated with the GPU entering and exiting the deep sleep mode.

Abstract: A technique is disclosed for a graphics processing unit (GPU) to enter and exit a power saving deep sleep mode. The technique involves preserving processing state within local memory by configuring the local memory to operate in a self-refresh mode while the GPU is powered off for deep sleep. An interface circuit coupled to the local memory is configured to prevent spurious GPU signals from disrupting proper self-refresh of the local memory. Spurious GPU signals may result from GPU power down and GPU power up events associated with the GPU entering and exiting the deep sleep mode.

Abstract: An apparatus and method for using non-power of two texture maps is described. Normalized texture map coordinates such as s and t are converted from a floating point format to a fixed point format and wrapping operations are performed to produce unnormalized texture map coordinates such as u and v corresponding to non-power of two texture maps.

Abstract: An apparatus and method for using non-power of two texture maps is described. Normalized texture map coordinates such as s and t are converted from a floating point format to a fixed point format and wrapping operations are performed to produce unnormalized texture map coordinates such as u and v corresponding to non-power of two texture maps.

Abstract: The present invention introduces circuitry and systems for performing two-dimensional motion compensation using a three-dimensional pipeline, as well as methods of operating the same. According to an exemplary embodiment, image processing circuitry is provided and includes both a two-dimensional image pipeline, which is operable to process two dimensional image data to generate successive two-dimensional image frames, and a three-dimensional image pipeline, which is operable to process three-dimensional image data to render successive three-dimensional image frames. The image processing circuitry further includes dual mode sub-processing circuitry, which is associated with each of the two- and three-dimensional image pipelines. The dual mode sub-processing circuitry is operable to perform motion compensation operations associated with the two-dimensional image pipeline in one mode and to perform rasterization operations associated the three-dimensional image pipeline in another mode.

Abstract: An N-way set associative virtual victim cache in which cache accesses are automatically directed only to the data array in the most recently used way. The cache memory comprises: 1) N ways, each of the N ways comprising a data array capable of storing L cache lines and a tag array capable of storing L address tags, each of the L address tags associated with one of the L cache lines; and 2) address decoding circuitry capable of receiving an incoming memory address and accessing a target cache line corresponding to the incoming memory address only in a most recently used one of the N ways.

Abstract: A dynamically configurable replacement technique in a unified or shared cache reduces domination by a particular functional unit or an application such as unified instruction/data caching by limiting the eviction ability to selected cache regions based on over utilization of the cache by a particular functional unit or application. A specific application includes a highly integrated multimedia processor employing a tightly coupled shared cache between central processing and graphics units wherein the eviction ability of the graphics unit is limited to selected cache regions when the graphics unit over utilizes the cache. Dynamic configurability can take the form of a programmable register that enables either one of a plurality of replacement modes based on captured statistics such as measurement of cache misses by a particular functional unit or application.

Abstract: The present invention provides a low-cost computer system which includes a single sharable block of memory that can be independently accessible as graphics memory or main store system memory without performance degradation. Because the “appetite” for main system memory (unlike that of a display memory) is difficult to satisfy, the memory can be addressed by reallocating an unused portion of a display memory for system memory use. Reallocation of the unused display memory alleviates any need to oversize the display memory, yet realizes the cost effectiveness of using readily available memory sizes. Further, reallocation of the graphics memory avoids any need to separately consider both the system memory and the display memory in accommodating worst case operational requirements. In accordance with additional embodiments, improved efficiency of operation can be achieved to enhance concurrency between plural banks of memory when expansion memory is included.

Abstract: A dynamically configurable replacement technique in a unified or shared cache reduces domination by a particular functional unit or an application such as unified instruction/data caching by limiting the eviction ability to selected cache regions based on over utilization of the cache by a particular functional unit or application. A specific application includes a highly integrated multimedia processor employing a tightly coupled shared cache between central processing and graphics units wherein the eviction ability of the graphics unit is limited to selected cache regions when the graphics unit over utilizes the cache. Dynamic configurability can take the form of a programmable register that enables either one of a plurality of replacement modes based on captured statistics such as measurement of cache misses by a particular functional unit or application.

Abstract: A Mini-PCI (MPCI) interface, and associated circuits and methods are provided for connecting a Peripheral Component Interconnect (PCI) device to one or more external devices. The MPCI interface, circuits and methods provide for a substantial if not full implementation of a PCI Local Bus without requiring the standard number of pins, traces, or signals. The MPCI interface includes a PCI/MPCI bridge connected between a PCI bus and to up to eight external devices in the form of MPCI devices and linear memory devices. The PCI/MPCI bridge is capable of receiving an incoming PCI transaction and multiplexing some of its signals together to create a corresponding incoming MPCI transaction. This incoming MPCI transaction may then be passed over an MPCI bus, having fewer lines and optimally operating at a higher frequency, the external devices. The process is reversed for outgoing transactions, i.e., the MPCI transactions are de-multiplexed to create PCI transactions.

Abstract: An improved bus architecture is provided in which the bus connects a single master to multiple targets including one primary target. Bus usage is predominately between the master and one primary target at a very high data transfer rate. Traffic between the master and other secondary targets has a much lower bandwidth requirement. The bus uses a single frequency clock for transfers involving the primary target and transfers involving the secondary targets. In accordance with one embodiment of the invention, the master is connected to the primary high bandwidth target using a high speed protocol and separate read and write data paths which are always driven (i.e., never tri-stated). Always driving the high speed data paths avoids the increased area and decreased performance that would be entailed by adding additional gating. The lower bandwidth targets are supported on a single bi-directional data path to minimize area.

Abstract: In a text mode of a display controller, for each character of the text, a plurality of multiple-byte words are stored in a memory buffer. Each multiple-byte word contains an ASCII character code for the character, font attribute information for the character and at least one font line for the character. For each character font line to be displayed on the monitor, a multiple byte word is read. The attribute information and a first character font line are extracted from the multiple byte word. The display controller then constructs a character scan line for the character based on the attribute information and the first character font line. The character scan line may then be displaying on the monitor.

Abstract: An integrated circuit with power conservation includes a number of functional blocks, each of which includes digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks.

Abstract: An image is written to a data frame buffer for display by a monitor. The image includes a repeated pattern. The present invention uses a repeated pattern cache which is not large enough to simultaneously contain an entire repeated pattern. When writing a pixel of the image, a horizontal pattern offset and a vertical pattern offset for a destination location of the pixel are determined. If a scan line for the repeated pattern which corresponds to the vertical pattern offset does not reside in the repeated pattern cache, the scan line for the repeated pattern which corresponds to the vertical pattern offset is fetched into the repeated pattern cache. When the scan line for the repeated pattern which corresponds to the vertical pattern offset resides in the repeated pattern cache, the pixel is accessed at a location in the repeated pattern cache at a location which corresponds to the horizontal pattern offset. The accessed pixel is written to the buffer.

Abstract: An integrated circuit with power conservation includes a number of functional blocks, each of which includes a digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks.