Patents by Inventor Rajeev Kumar Ranjan

Rajeev Kumar Ranjan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9477802
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: October 25, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Kathryn Drews Kranen, Beth C. Isaksen, Georgia Penido Safe
  • Patent number: 9342638
    Abstract: An improved approach is provided to implement performance checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis, where the two designs are checked to see if they are equivalent on the transaction-level. Thereafter, the outputs for the transactions are analyzed relative to delay time periods, which allows verification and identification of possible performance issues and differences between the two designs.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: May 17, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Antonio Celso Caldeira, Jr., Rajeev Kumar Ranjan, Marcus Vinicius da Mata Gomes
  • Patent number: 8831925
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: September 9, 2014
    Assignee: Jasper Design Automation, Inc.
    Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Lawrence Loh, Beth C. Isaksen, Yann Alain Antonioli, Craig Franklin Deaton
  • Patent number: 8731894
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 20, 2014
    Assignee: Jasper Design Automation, Inc.
    Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Lawrence Loh, Beth C. Isaksen, Yann Alain Antonioli, Craig Franklin Deaton
  • Patent number: 8630824
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: January 14, 2014
    Assignee: Jasper Design Automation, Inc.
    Inventors: Chung-Wah Norris Ip, Kathryn Drews Kranen, Rajeev Kumar Ranjan, Beth C. Isaksen, Karl Stefan Esbjörner, Craig Franklin Deaton
  • Patent number: 8527911
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: September 3, 2013
    Assignee: Jasper Design Automation, Inc.
    Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Georgia Penido Safe, Claudionor José Nunes Coelho, Yann Alain Antonioli
  • Patent number: 8458621
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: June 4, 2013
    Assignee: Jasper Design Automation, Inc.
    Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Georgia Penido Safe, Claudionor José Nunes Coelho, Yann Alain Antonioli
  • Patent number: 8205187
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: June 19, 2012
    Assignee: Jasper Design Automation, Inc.
    Inventors: Claudionor José Nunes Coelho, Chung-Wah Norris Ip, Harry David Foster, Rajeev Kumar Ranjan, Kathryn Drews Kranen, Georgia Penido Safe
  • Patent number: 7092858
    Abstract: In a finite state machine (FSMverify) a set of goal states, to be searched for their reachability from a start state, is defined. An overapproximated path is found from a start state to a goal state by a forward approximation technique. The overapproximated path representation relies upon a partitioning of the state and input bits of FSMverify. A state matrix of the overapproximated path is organized by time-steps of FSMverify along a first dimension and by partitions of FSMverify state bits along a second dimension. An underapproximated path, along the path of the stepping stone matrix, is determined. Underapproximation is typically accomplished by simulation. A sequence of states to be output is updated with the underapproximated path. If a start to goal state sequence has been found, the procedure ends. Otherwise, the above steps of over and under approximation are repeated, using the results of the last underapproximation as a start state.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: August 15, 2006
    Assignee: Synopsys, Inc.
    Inventors: James Herbert Kukula, Thomas Robert Shiple, Rajeev Kumar Ranjan
  • Patent number: 6539523
    Abstract: A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, a comprehensive set of design verification checks may be formulated by applying predetermined properties to an annotated hardware design representation. Information regarding the intended flow of logical signals in the hardware design is received by way of annotations in a control file or annotations embedded in the hardware design representation itself. The annotations include (1) an indication of one or more variables in the representation of the hardware design through which the logical signals pass, and (2) an indication of one or more conditions under which each of the one or more variables are to be associated with each of a set of states. Checks are then automatically formulated based upon a predetermined set of properties that must hold true in order for the hardware design to operate in accordance with the intended flow.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: March 25, 2003
    Assignee: Real Intent, Inc.
    Inventors: Prakash Narain, Jay Andrew Littlefield, Christopher Richard Morrison, Rajeev Kumar Ranjan