Patents by Inventor Rajeev Nagabhirava
Rajeev Nagabhirava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200409843Abstract: The present disclosure generally relates to a method and device for reduce the amount of energy used to revert data within a storage device to a consistent state after a power loss event. Once power is lost from a host device, and prior to complete shutdown, a log is created within non-volatile memory (NVM) of the storage device. The log contains logical block addresses (LBAs) corresponding to data that experienced a write failure. At the next power-on event, the log is checked to see if any LBAs are present. If LBAs are present in the log, then the data that experienced a write failure can be properly written to the storage device.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Inventors: Rajeev NAGABHIRAVA, Avichay Haim HODES, Judah Gamliel HAHN
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Patent number: 10459787Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.Type: GrantFiled: September 20, 2017Date of Patent: October 29, 2019Assignee: SanDisk Technologies LLCInventors: Damian Yurzola, Eran Sharon, Idan Alrod, Michael Altshuler, Madhuri Kotagiri, Rajeev Nagabhirava
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Patent number: 9965186Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.Type: GrantFiled: March 7, 2017Date of Patent: May 8, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Arjun Kapoor, Rajeev Nagabhirava, Dhaval Parikh
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Publication number: 20180024880Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.Type: ApplicationFiled: September 20, 2017Publication date: January 25, 2018Inventors: Damian Yurzola, Eran Sharon, Idan Alrod, Michael Altshuler, Madhuri Kotagiri, Rajeev Nagabhirava
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Patent number: 9792174Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.Type: GrantFiled: August 31, 2015Date of Patent: October 17, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Damian Pablo Yurzola, Eran Sharon, Idan Alrod, Michael Altshuler, Madhuri Kotagiri, Rajeev Nagabhirava
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Publication number: 20170177231Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.Type: ApplicationFiled: March 7, 2017Publication date: June 22, 2017Inventors: Arjun Kapoor, Rajeev Nagabhirava, Dhaval Parikh
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Patent number: 9607664Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.Type: GrantFiled: September 27, 2007Date of Patent: March 28, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Arjun Kapoor, Rajeev Nagabhirava, Dhaval Parikh
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Patent number: 9466383Abstract: A nonvolatile memory is organized into blocks as erase units and physical pages as read/write units. A host addresses data by logical pages, which are storable in corresponding physical pages. Groups of logical pages may be further aggregated into logical groups as addressing units. The memory writes host data in either first or second write streams, writing to respective blocks either logical-group by logical-group or logical-page by logical-page in order to reduce the size of logical-to-physical-address maps that are cached in a controller random-access memory (RAM). A group-level map may be used to track logical groups. A page-level map may be used to track logical pages. Only one block at a time needs be open in the second stream to accept logical pages from multiple logical groups that are active. Garbage collection is performed on the blocks from each write stream independently without data copying between the two streams.Type: GrantFiled: December 30, 2013Date of Patent: October 11, 2016Assignee: SanDisk Technologies LLCInventors: Yong Peng, Rajeev Nagabhirava
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Patent number: 9455048Abstract: Systems and methods for improving NAND flash memory yields by identifying memory blocks with benign word line defects. Memory blocks including word line defects may be classified as incomplete memory blocks and may be used for storing data fragments. A data fragment may correspond with data written into memory cells associated with one or more contiguous word lines within a memory block that does not include a bad word line. In some cases, firmware associated with a NAND flash memory device may identify one or more data fragments based on the location of bad word lines within a memory block. A word line defect may be considered a benign defect if the defect does not prevent memory cells connected to other word lines within a memory block from being programmed and/or read reliably.Type: GrantFiled: June 28, 2013Date of Patent: September 27, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Tucker Dean Berckmann, Talal Ahwal, Damian Yurzola, Krishnamurthy Dhakshinamurthy, Yong Peng, Rajeev Nagabhirava, Arjun Hary, Tal Heller, Yigal Eli
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Publication number: 20150370632Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Inventors: Damian Pablo Yurzola, Eran Sharon, ldan Alrod, Michael Altshuler, Madhuri Kotagiri, Rajeev Nagabhirava
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Patent number: 9146807Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.Type: GrantFiled: March 11, 2013Date of Patent: September 29, 2015Assignee: SanDisk Technologies Inc.Inventors: Damian Pablo Yurzola, Eran Sharon, Idan Alrod, Michael Altshuler, Madhuri Kotagiri, Rajeev Nagabhirava
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Publication number: 20150186270Abstract: A nonvolatile memory is organized into blocks as erase units and physical pages as read/write units. A host addresses data by logical pages, which are storable in corresponding physical pages. Groups of logical pages are further aggregated into ogical groups as addressing units. The memory writes host data in either first or second write streams, writing to respective blocks either logical-group by logical-group or logical-page by logical-page in order to reduce the size of logical-to-physical-address maps that are cached in a controller RAM. Only one block at a time needs be open in the second stream to accept logical pages from multiple logical groups that are active. Garbage collection is performed on the blocks from each write stream independently without data copying between the two streams.Type: ApplicationFiled: December 30, 2013Publication date: July 2, 2015Applicant: SanDisk Technologies Inc.Inventors: Yong Peng, Rajeev Nagabhirava
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Publication number: 20150169228Abstract: A data storage device includes a controller coupled to a non-volatile memory that includes a plurality of dies. The plurality of dies includes a first die and a second die. The controller is configured to receive data to be stored into the non-volatile memory and to partition the data into a first portion and a second portion. The controller is further configured to store the first portion into the first die and to store the second portion into the second die. The first portion is stored into the first die using a single-bit mode. The second portion is stored into the second die using a multi-bit mode.Type: ApplicationFiled: February 10, 2014Publication date: June 18, 2015Applicant: Sandisk Technologies Inc.Inventors: VIJAY SIVASANKARAN, ABHIJEET MANOHAR, RAJEEV NAGABHIRAVA, KIRAN KUMAR MURALIDHARAN
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Publication number: 20150003156Abstract: Methods for improving NAND flash memory yields by identifying memory blocks with benign word line defects are described. Memory blocks including word line defects may be classified as incomplete memory blocks and may be used for storing data fragments. A data fragment may correspond with data written into memory cells associated with one or more contiguous word lines within a memory block that does not include a bad word line. In some cases, firmware associated with a NAND flash memory device may identify one or more data fragments based on the location of bad word lines within a memory block. A word line defect may be considered a benign defect if the defect does not prevent memory cells connected to other word lines within a memory block from being programmed and/or read reliably.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Tucker Dean Berckmann, Talal Ahwal, Damian Yurzola, Krishnamurthy Dhakshinamurthy, Yong Peng, Rajeev Nagabhirava, Arjun Hary, Tal Heller, Yigal Eli
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Publication number: 20140237167Abstract: Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system.Type: ApplicationFiled: April 25, 2014Publication date: August 21, 2014Applicant: SanDisk Technologies Inc.Inventors: Damian P. Yurzola, Rajeev Nagabhirava, Gary J. Lin, Matthew Davidson, Paul A. Lassa
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Publication number: 20140189201Abstract: A system having a split bus flash memory and a method for operating the split bus flash memory is disclosed. The system may include a controller, a non-volatile memory (including first and second non-volatile memory chips) and the system bus. The controller is configured to communicate via an N-bit bus. The first and second non-volatile memory chips are configured to communicate via an M-bit bus, with M<N. The system bus connects the controller with the first and second non-volatile memory chips, wherein the system bus is split with some of the system bus lines connected to the first non-volatile memory chip and other of the system bus lines connected to the second non-volatile memory chip. In this way, the controller may communicate command, address and/or data with the memory chips in parallel.Type: ApplicationFiled: March 11, 2013Publication date: July 3, 2014Inventors: Krishnamurthy Dhakshinamurthy, Rajeev Nagabhirava, Tony Ahwal, Leeladhar Agarwal, Piyush Anil Dhotre
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Publication number: 20140157087Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.Type: ApplicationFiled: March 11, 2013Publication date: June 5, 2014Applicant: SanDisk Technologies, Inc.Inventors: Damian Pablo Yurzola, Eran Sharon, Idan Alrod, Michael Altshuler, Madhuri Kotagiri, Rajeev Nagabhirava
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Patent number: 8745369Abstract: Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system.Type: GrantFiled: November 15, 2011Date of Patent: June 3, 2014Assignee: SanDisk Technologies, Inc.Inventors: Damian P Yurzola, Rajeev Nagabhirava, Gary J Lin, Matthew Davidson, Paul A Lassa
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Publication number: 20140047159Abstract: A server system, such as an enterprise server, may include an array of memory devices. The memory devices may include non-volatile or flash memory and be referred to as flash storage modules (“FSM”). The server system includes a host computer or host server that communicates with the array of FSM. The host may include a media management layer or flash transformation layer that is implemented by drivers on the host for controlling the FSM.Type: ApplicationFiled: August 10, 2012Publication date: February 13, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: Tony Ahwal, Yong Peng, Rajeev Nagabhirava
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Patent number: 8533564Abstract: A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array.Type: GrantFiled: December 23, 2009Date of Patent: September 10, 2013Assignee: Sandisk Technologies Inc.Inventors: Damian Pablo Yurzola, Rajeev Nagabhirava, Arjun Kapoor, Itai Dror