Abstract: The present disclosure generally relates to sensor device, such as a magnetic sensor bridge, that utilizes a dual free layer (DFL) structure. The device includes a plurality of resistors that each includes the same DFL structure. Adjacent the DFL structure is a magnetic structure that can include a permanent magnet, an antiferromagnetic (AFM) layer having a synthetic AFM (SAF) structure thereon, a permanent magnetic having a SAF structure thereon, or an AFM layer having a ferromagnetic layer thereon. The DFL structures are aligned with different layers of the magnetic structures to differentiate the resistors. The different alignment and/or different magnetic structures result in a decrease in production time due to reduced complexity and, thus, reduces costs.

Abstract: Aspects of the present disclosure generally relate to optical devices and related methods that facilitate tilt in camera systems, such as tilt of a lens. In one example, an optical device includes a lens, an image sensor disposed below the lens, a plurality of magnets disposed about the lens, and a plurality of: (1) vertical coil structures coiled in one or more vertical planes and (2) horizontal coil structures coiled in one or more horizontal planes. When power is applied, the coil structures can generate magnetic fields that, in the presence of the magnets, cause relative movement of the coil structures and associated structures. The plurality of vertical coil structures are configured to horizontally move the lens. The plurality of horizontal coil structures are configured to tilt the lens when differing electrical power is applied to at least two of the plurality of horizontal coil structures.

Abstract: Aspects of the present disclosure generally relate to optical devices and related methods that facilitate tilt in camera systems, such as tilt of a lens. In one example, an optical device includes a lens, an image sensor disposed below the lens, a plurality of magnets disposed about the lens, and a plurality of: (1) vertical coil structures coiled in one or more vertical planes and (2) horizontal coil structures coiled in one or more horizontal planes. When power is applied, the coil structures can generate magnetic fields that, in the presence of the magnets, cause relative movement of the coil structures and associated structures. The plurality of vertical coil structures are configured to horizontally move the lens. The plurality of horizontal coil structures are configured to tilt the lens when differing electrical power is applied to at least two of the plurality of horizontal coil structures.

Abstract: The present disclosure generally relates to a method and device for reduce the amount of energy used to revert data within a storage device to a consistent state after a power loss event. Once power is lost from a host device, and prior to complete shutdown, a log is created within non-volatile memory (NVM) of the storage device. The log contains logical block addresses (LBAs) corresponding to data that experienced a write failure. At the next power-on event, the log is checked to see if any LBAs are present. If LBAs are present in the log, then the data that experienced a write failure can be properly written to the storage device.

Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.

Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.

Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.

Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.

Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.

Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.

Abstract: A nonvolatile memory is organized into blocks as erase units and physical pages as read/write units. A host addresses data by logical pages, which are storable in corresponding physical pages. Groups of logical pages may be further aggregated into logical groups as addressing units. The memory writes host data in either first or second write streams, writing to respective blocks either logical-group by logical-group or logical-page by logical-page in order to reduce the size of logical-to-physical-address maps that are cached in a controller random-access memory (RAM). A group-level map may be used to track logical groups. A page-level map may be used to track logical pages. Only one block at a time needs be open in the second stream to accept logical pages from multiple logical groups that are active. Garbage collection is performed on the blocks from each write stream independently without data copying between the two streams.

Abstract: Systems and methods for improving NAND flash memory yields by identifying memory blocks with benign word line defects. Memory blocks including word line defects may be classified as incomplete memory blocks and may be used for storing data fragments. A data fragment may correspond with data written into memory cells associated with one or more contiguous word lines within a memory block that does not include a bad word line. In some cases, firmware associated with a NAND flash memory device may identify one or more data fragments based on the location of bad word lines within a memory block. A word line defect may be considered a benign defect if the defect does not prevent memory cells connected to other word lines within a memory block from being programmed and/or read reliably.

Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.

Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.

Abstract: A nonvolatile memory is organized into blocks as erase units and physical pages as read/write units. A host addresses data by logical pages, which are storable in corresponding physical pages. Groups of logical pages are further aggregated into ogical groups as addressing units. The memory writes host data in either first or second write streams, writing to respective blocks either logical-group by logical-group or logical-page by logical-page in order to reduce the size of logical-to-physical-address maps that are cached in a controller RAM. Only one block at a time needs be open in the second stream to accept logical pages from multiple logical groups that are active. Garbage collection is performed on the blocks from each write stream independently without data copying between the two streams.

Abstract: A data storage device includes a controller coupled to a non-volatile memory that includes a plurality of dies. The plurality of dies includes a first die and a second die. The controller is configured to receive data to be stored into the non-volatile memory and to partition the data into a first portion and a second portion. The controller is further configured to store the first portion into the first die and to store the second portion into the second die. The first portion is stored into the first die using a single-bit mode. The second portion is stored into the second die using a multi-bit mode.

Abstract: Methods for improving NAND flash memory yields by identifying memory blocks with benign word line defects are described. Memory blocks including word line defects may be classified as incomplete memory blocks and may be used for storing data fragments. A data fragment may correspond with data written into memory cells associated with one or more contiguous word lines within a memory block that does not include a bad word line. In some cases, firmware associated with a NAND flash memory device may identify one or more data fragments based on the location of bad word lines within a memory block. A word line defect may be considered a benign defect if the defect does not prevent memory cells connected to other word lines within a memory block from being programmed and/or read reliably.

Abstract: Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system.

Abstract: A system having a split bus flash memory and a method for operating the split bus flash memory is disclosed. The system may include a controller, a non-volatile memory (including first and second non-volatile memory chips) and the system bus. The controller is configured to communicate via an N-bit bus. The first and second non-volatile memory chips are configured to communicate via an M-bit bus, with M<N. The system bus connects the controller with the first and second non-volatile memory chips, wherein the system bus is split with some of the system bus lines connected to the first non-volatile memory chip and other of the system bus lines connected to the second non-volatile memory chip. In this way, the controller may communicate command, address and/or data with the memory chips in parallel.

Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.