Patents by Inventor Rajeev Patwari

Rajeev Patwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240045692
    Abstract: Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions based on the replica of the register address space. The transaction instructions and the wait instructions are included in an instruction buffer. The instruction buffer is provided to a microcontroller configured to execute the transaction instructions and the wait instructions to implement the runtime data movements for the design as implemented in the DP array. In another aspect, the instruction buffer is stored in a file for subsequent execution by the microcontroller.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Applicant: Xilinx, Inc.
    Inventors: Xiao Teng, Tejus Siddagangaiah, Bryan Lozano, Ehsan Ghasemi, Rajeev Patwari, Elliott Delaye, Jorn Tuyls, Aaron Ng, Sanket Pandit, Pramod Peethambaran, Satyaprakash Pareek
  • Publication number: 20240028556
    Abstract: An integrated circuit includes a plurality of kernels and a virtual machine coupled to the plurality of kernels. The virtual machine is configured to interpret instructions directed to different ones of the plurality of kernels. The virtual machine is configured to control operation of the different ones of the plurality of kernels responsive to the instructions.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Applicant: Xilinx, Inc.
    Inventors: Sanket Pandit, Jorn Tuyls, Xiao Teng, Rajeev Patwari, Ehsan Ghasemi, Elliott Delaye, Aaron Ng
  • Publication number: 20230401480
    Abstract: Hardware acceleration of machine learning (ML) designs includes translating an ML primitive into an intermediate representation. The intermediate representation is subdivided to specify a functional compute block. The functional compute block is sized according to a compute node primitive adapted for implementing the ML primitive on target hardware. An overlay is generated for the ML primitive, at least in part, by mapping the functional compute block to the compute node primitive. The overlay is synthesizable to implement the ML primitive on the target hardware. The overlay can be scheduled for operation within the target hardware as part of an ML design including the ML primitive.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Applicant: Xilinx, Inc.
    Inventors: Ehsan Ghasemi, Rajeev Patwari, Elliott Delaye, Jorn Tuyls, Ephrem C. Wu, Xiao Teng, Sanket Pandit
  • Publication number: 20230297824
    Abstract: A programmable, non-linear (PNL) activation engine for a neural network is capable of receiving input data within a circuit. In response to receiving an instruction corresponding to the input data, the PNL activation engine is capable of selecting a first non-linear activation function from a plurality of non-linear activation functions by decoding the instruction. The PNL activation engine is capable of fetching a first set of coefficients corresponding to the first non-linear activation function from a memory. The PNL activation engine is capable of performing a polynomial approximation of the first non-linear activation function on the input data using the first set of coefficients. The PNL activation engine is capable of outputting a result from the polynomial approximation of the first non-linear activation function.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Applicant: Xilinx, Inc.
    Inventors: Rajeev Patwari, Chaithanya Dudha, Jorn Tuyls, Kaushik Barman, Aaron Ng
  • Publication number: 20230185451
    Abstract: Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Applicant: Xilinx, Inc.
    Inventors: Vamsi Krishna Nalluri, Sai Lalith Chaitanya Ambatipudi, Mrinal J. Sarmah, Rajeev Patwari, Shreyas Manjunath, Sandeep Jayant Sathe
  • Patent number: 11188697
    Abstract: Determining on-chip memory access patterns can include modifying a circuit design to include a profiler circuit for a random-access memory (RAM) of the circuit design, wherein the profiler circuit is configured to monitor an address bus of the RAM, and modifying the circuit design to include a debug circuit connected to the profiler circuit. Usage data for the RAM can be generated by detecting, using the profiler circuit, addresses of the RAM accessed during a test of the circuit design, as implemented in an integrated circuit. The usage data for the RAM can be output using the debug circuit.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: November 30, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chaithanya Dudha, Rajeev Patwari, Nithin Kumar Guggilla, Ashish Sirasao, Krishna Garlapati