Abstract: Systems and methods are provided for selecting colony locations. Selecting colony locations can include determine a location of a selection tool on a culture plate image, determining a location of a potential source of error on the culture plate image, comparing the location of the selection tool to the location of the potential source of error; and determining an error when the location of the selection tool overlays the location of the potential source of error.

Abstract: Systems and methods are provided for selecting colony locations. Selecting colony locations can include determine a location of a selection tool on a culture plate image, determining a location of a potential source of error on the culture plate image, comparing the location of the selection tool to the location of the potential source of error; and determining an error when the location of the selection tool overlays the location of the potential source of error.

Abstract: Systems and methods are provided for selecting colony locations. Selecting colony locations can include determine a location of a selection tool on a culture plate image, determining a location of a potential source of error on the culture plate image, comparing the location of the selection tool to the location of the potential source of error; and determining an error when the location of the selection tool overlays the location of the potential source of error.

Abstract: Systems and methods are provided for selecting colony locations. Selecting colony locations can include determine a location of a selection tool on a culture plate image, determining a location of a potential source of error on the culture plate image, comparing the location of the selection tool to the location of the potential source of error; and determining an error when the location of the selection tool overlays the location of the potential source of error.

Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate a validation system into a circuit design. The validation system can be configured to monitor at least a portion of an electronic device described in the circuit design. The tools and mechanisms can identify one or more trace signals associated with the electronic device to route to the validation system, and identify one or more trigger signals associated with the electronic device to route to the validation system. The tools and mechanisms can configure the validation system to detect a conditional event corresponding a state of the one or more trigger signals, and to transmit the trace signals associated with the electronic device for debugging in response to the detected conditional event.

Abstract: This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Abstract: This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate a validation system into a circuit design. The validation system can be configured to monitor at least a portion of an electronic device described in the circuit design. The tools and mechanisms can identify one or more trace signals associated with the electronic device to route to the validation system, and identify one or more trigger signals associated with the electronic device to route to the validation system. The tools and mechanisms can configure the validation system to detect a conditional event corresponding a state of the one or more trigger signals, and to transmit the trace signals associated with the electronic device for debugging in response to the detected conditional event.

Abstract: This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Abstract: The invention concerns the generation of schematics from analog netlists. Various implementations of the invention provide that an analog netlist defining a number of hardware components and the connectivity between the hardware components is identified. Subsequently, the netlist is sorted and partitioned into component groups. The component groups are arranged and lines are routed between the component groups. The corresponding hardware components are arranged within the component groups and a schematic corresponding to the arranged hardware components is generated.

Abstract: The invention concerns the generation of schematics from analog netlists. Various implementations of the invention provide that an analog netlist defining a number of hardware components and the connectivity between the hardware components is identified. Subsequently, the netlist is sorted and partitioned into component groups. The component groups are arranged and lines are routed between the component groups. The corresponding hardware components are arranged within the component groups and a schematic corresponding to the arranged hardware components is generated.

Abstract: A system for responding to failures of connections in a network. In one embodiment, there is a system for responding to destination failures involving SPVx (switched-permanent virtual circuit) connections includes a primary source node. The system includes a primary source switch for producing an SPVx connection, the primary source node in communication with the primary source switch. The system includes a primary destination node. The system includes a primary destination switch for receiving the SPVx connection, the primary destination node in communication with the primary destination switch, the connection following a primary path between the primary source node and the primary destination node. The system includes an alternate destination node. The primary destination switch redirects automatically the primary connection to the alternate destination node along an alternate path when the primary destination switch detects a failure of the primary path.

Abstract: A system for responding to failures of connections in a network. A system for responding to destination failures involving SPVx connections. A system for responding to source failures involving SPVx connections A system for responding to failures involving SPVx connections. A method for responding to failures involving SPVx connections. A method for responding to destination failures involving SPVx connections. A method for responding to source failures involving SPVx connections. A method for responding to failures of connections in a network.