Patents by Inventor Rajeev SIVADASAN

Rajeev SIVADASAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240385142
    Abstract: A visualization of electrical continuity test results for a transducer tile array may be generated according to embodiments herein. The visualization may include an indication, for each channel under test, of whether the channel passed or failed the continuity test, and an indication of whether the transducer tile array is determined to be functional.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Applicant: Exo Imaging, Inc.
    Inventors: Mohammad Afrough, Rajeev Sivadasan, Jed Davidow, Gordon T. Sasamori
  • Patent number: 12053330
    Abstract: Described herein are methods and systems for testing transducers and associated integrated circuits. In some cases, a method or system described herein can comprise modulating a bias voltage using a test signal in order to produce a modulated bias voltage signal useful in testing a plurality of transducers of a transducer array in parallel.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: August 6, 2024
    Assignee: Exo Imaging, Inc.
    Inventors: Jonathan Strode, Rajeev Sivadasan, Gordon Sasamori
  • Publication number: 20220409184
    Abstract: Described herein are methods and systems for testing transducers and associated integrated circuits. In some cases, a method or system described herein can comprise modulating a bias voltage using a test signal in order to produce a modulated bias voltage signal useful in testing a plurality of transducers of a transducer array in parallel.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: Jonathan STRODE, Rajeev SIVADASAN, Gordon SASAMORI