Abstract: An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.

Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.

Abstract: A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task.

Abstract: An apparatus includes a controller and logic circuitry. The controller is configured to generate multiple single-bit logic values. Each single-bit logic value has one of (i) a first value indicating that a data packet has been written into a memory and (ii) a second value indicating that a data packet has been read from the memory. The logic circuitry is configured to serially stack the single-bit logic values. The apparatus could further include a shift memory bank configured to store the single-bit logic values. The logic circuitry can be configured to serially stack the single-bit logic values in the shift memory bank. For example, the logic circuitry can be configured to shift the single-bit logic values in the shift memory bank in different directions and insert one single-bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value.

Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.

Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.

Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.

Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

Abstract: An apparatus includes a controller and logic circuitry. The controller is configured to generate multiple single-bit logic values. Each single-bit logic value has one of (i) a first value indicating that a data packet has been written into a memory and (ii) a second value indicating that a data packet has been read from the memory. The logic circuitry is configured to serially stack the single-bit logic values. The apparatus could further include a shift memory bank configured to store the single-bit logic values. The logic circuitry can be configured to serially stack the single-bit logic values in the shift memory bank. For example, the logic circuitry can be configured to shift the single-bit logic values in the shift memory bank in different directions and insert one single-bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value.

Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

Abstract: A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task.

Abstract: A system includes a bus slave coupled to a plurality of bus masters via one or more interconnects. The system also includes a memory protection unit (MPU) associated with the bus slave, the MPU having a set of access permissions that grants access to the bus slave from a first bus master and denies access to the bus slave from a second bus master. The MPU generates an error response as result of a transaction generated by a task on the second bus master attempting to access the bus slave.

Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.