Patents by Inventor Rajeeva Krishna

Rajeeva Krishna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240362173
    Abstract: A microprocessor-PLD hybrid architecture includes an IPC microprocessor and a PLD in signal communication with the IPC microprocessor via an IPC interface. The IPC microprocessor outputs a data read command to initiate a data read operation or a data write command. The PLD includes a plurality of PLD modules that store data and a bus controller. The bus controller communicates with the plurality of PLD modules via a plurality of PLD interfaces and is configured to sequentially execute a set of bus controller instructions. The bus controller reads data from a target PLD module from among the plurality of PLD modules in response to receiving the data read command, and transfers the data to the IPC microprocessor. The bus controller receives data from the IPC microprocessor and stores the data in a target PLD module from among the plurality of PLD modules in response to receiving the data write command.
    Type: Application
    Filed: September 27, 2023
    Publication date: October 31, 2024
    Inventors: Rajesh Madathikandam, Robin David Hill, Stephen Potter, Ashish Vijay, Rajeeva Krishna, Anitha Thangavel
  • Publication number: 20240345984
    Abstract: A bus controller-based page memory programmable logic device (PLD) architecture includes a plurality of PLD modules and a bus controller in signal communication with the plurality of PLD modules via a universal bus interface. Each PLD module include a PLD memory unit configured to store first data. The bus controller includes bus memory unit configured to store second data and includes a bus controller engine configured to sequentially execute a set of bus controller instructions. One or both of the first data and the second data is transferred between the bus controller and a target PLD module among the plurality of PLD modules in response to sequentially executing the set of bus controller instructions.
    Type: Application
    Filed: October 23, 2023
    Publication date: October 17, 2024
    Inventors: Rajesh Madathikandam, Robin David Hill, Ashish Vijay, Stephen Potter, Rajeeva Krishna, Anitha Thangavel
  • Publication number: 20240319699
    Abstract: A bus controller-based programmable logic device (PLD) architecture is provided and includes a dual-port unit interposed between bus controllers. The dual port unit includes first and second data transfer layers. The first data transfer layer includes write and read areas for data transfer between the first and second bus controllers, respectively. A write to the read area is prevented during a read by the second bus controller. The second data transfer layer includes read and write areas for data transfer between the first and second bus controllers, respectively. A write to the read area is prevented during a read by the first bus controller.
    Type: Application
    Filed: May 19, 2023
    Publication date: September 26, 2024
    Inventors: Rajeeva Krishna, Robin David Hill, Stephen Potter, Ashish Vijay, Rajesh Madathikandam