Patents by Inventor Rajeewa R. Arya

Rajeewa R. Arya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080264483
    Abstract: An amorphous silicon photovoltaic cell exhibiting improved light trapping, and a method for generating electricity from sunlight therewith. The cell comprises a plurality of layers, including a transparent superstrate; a specular, first transparent conductor positioned below the transparent superstrate; at least one p-i-n structure having an active layer positioned below the first transparent conductor; a second transparent conductor positioned below the p-i-n structure; and a layer of transparent material positioned below the second transparent conductor. The layer of transparent material may be textured amorphous silicon having a relatively high dielectric constant. The cell may further include a back coating positioned below the layer of transparent material, and a back reflector positioned below the back coating layer.
    Type: Application
    Filed: October 19, 2007
    Publication date: October 30, 2008
    Inventors: Marvin S. Keshner, Paul McClelland, Rajeewa R. Arya
  • Patent number: 6368892
    Abstract: Efficient broader spectrum monolithic solar cells are produced by coupling a CIS or CIGS polycrystalline semiconductor to an amorphous silicon semiconductor. Coupling can be accomplished with a n-type conductor, such as cadmium sulfide or microcrystalline n-duped amorphous silicon. Cadmium sulfide can be deposited on the CIS or CIGS polycrystalline semiconductor by solution growth, sputtering or evaporation. A transparent conductive oxide can be deposited on the cadmium sulfide by low pressure chemical vapor deposition. The microcrystalline n-doped amorphous silicon and the amorphous silicon semiconductor can be deposited by enhanced plasma chemical vapor deposition. The amorphous silicon can comprise: hydrogenated amorphous silicon, hydrogenated amorphous silicon carbon, or hydrogenated amorphous silicon germanium. Triple junction solar cells can be produced with an amorphous silicon front cell, an amorphous silicon germanium middle cell, and a CIS or CIGS polycrystalline back cell, on a substrate.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: April 9, 2002
    Assignee: BP Corporation North America Inc.
    Inventor: Rajeewa R. Arya
  • Patent number: 6121541
    Abstract: Efficient broader spectrum monolithic solar cells are produced by coupling a CIS or CIGS polycrystalline semiconductor to an amorphous silicon semiconductor. Coupling can be accomplished with a n-type conductor, such as cadmium sulfide or microcrystalline n-doped amorphous silicon. Cadmium sulfide can be deposited on the CIS or CIGS polycrystalline semiconductor by solution growth, sputtering or evaporation. A transparent conductive oxide can be deposited on the cadmium sulfide by low pressure chemical vapor deposition. The microcrystalline n-doped amorphous silicon and the amorphous silicon semiconductor can be deposited by enhanced plasma chemical vapor deposition. The amorphous silicon can comprise: hydrogenated amorphous silicon, hydrogenated amorphous silicon carbon, or hydrogenated amorphous silicon germanium. Triple junction solar cells can be produced with an amorphous silicon front cell, an amorphous silicon germanium middle cell, and a CIS or CIGS polycrystalline back cell, on a substrate.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: September 19, 2000
    Assignee: BP Solarex
    Inventor: Rajeewa R. Arya
  • Patent number: 5246506
    Abstract: A multijunction photovoltaic device includes first and second amorphous silicon PIN photovoltaic cells in a stacked arrangement. An interface layer, composed of a doped silicon compound, is disposed between the two cells and has a lower bandgap than the respective n- and p-type adjacent layers of the first and second cells. The interface layer forms an ohmic contact with the one or the adjacent cell layers of the same conductivity type, and a tunnel junction with the other of the adjacent cell layers. The disclosed device is fabricated by a glow discharge process.
    Type: Grant
    Filed: July 16, 1991
    Date of Patent: September 21, 1993
    Assignee: Solarex Corporation
    Inventors: Rajeewa R. Arya, Anthony W. Catalano
  • Patent number: 5055141
    Abstract: A photovoltaic cell that includes a transparent substrate, a front conductive layer formed on the substrate, a p-type layer formed on the front conductive layer, an i-layer of amorphous silicon formed on the p-layer, a wide bandgap n-type layer formed on the i-layer and a back contact layer formed on the n-type structure. The wide bandgap n-type layer may be an n-type sandwich structure which includes first, second, and third n-layers successively formed on one another. The first n-layer is formed on the i-layer, the second n-layer is formed on the first n-layer, and the n-layer is formed on the second n-layer. The second n-layer has an optical bandgap wider than the optical bandgap of the first and second n-type layers.
    Type: Grant
    Filed: January 19, 1990
    Date of Patent: October 8, 1991
    Assignee: Solarex Corporation
    Inventors: Rajeewa R. Arya, Anthony W. Catalano
  • Patent number: 4749454
    Abstract: A method of removing electrical shorts and shunts from a thin-film semiconductor device having pairs of electrodes with exposed contact surfaces wherein each pair of electrodes is separated by a semiconductor film. The disclosed method comprises the steps of coating the exposed contact surfaces with an ionic solution and successively applying a reverse-bias voltage between the exposed contact surfaces of each pair of electrodes. The ionic solution has an etching rate that increases with increased temperature so that the leakage current flowing through shorts and shunts located between each respective pair of electrodes in response to the reverse-bias voltage will create a local temperature increase at the shorts and shunts and selectively etch or oxidize the shorts and shunts, rendering them substantially nonconductive. The exposed contact surfaces can be coated using a sponge applicator or spray apparatus.
    Type: Grant
    Filed: November 17, 1986
    Date of Patent: June 7, 1988
    Assignee: Solarex Corporation
    Inventors: Rajeewa R. Arya, Robert S. Oswald
  • Patent number: 4718947
    Abstract: Superlattice doped layers for amorphous silicon photovoltaic cells comprise a plurality of first and second lattices of amorphous silicon alternatingly formed on one another. Each of the first lattices has a first optical bandgap and each of the second lattices has a second optical bandgap different from the first optical bandgap. A method of fabricating the superlattice doped layers also is disclosed.
    Type: Grant
    Filed: April 17, 1986
    Date of Patent: January 12, 1988
    Assignee: Solarex Corporation
    Inventor: Rajeewa R. Arya