Patents by Inventor Rajen Chanchani

Rajen Chanchani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8597985
    Abstract: In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predetermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 3, 2013
    Assignee: Sandia Corporation
    Inventors: Rajen Chanchani, Christopher Nordquist, Roy H. Olsson, Tracy C. Peterson, Randy J. Shul, Catalina Ahlers, Thomas A. Plut, Gary A. Patrizi
  • Patent number: 7335972
    Abstract: A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: February 26, 2008
    Assignee: Sandia Corporation
    Inventor: Rajen Chanchani
  • Publication number: 20070158787
    Abstract: A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.
    Type: Application
    Filed: November 13, 2003
    Publication date: July 12, 2007
    Inventor: Rajen Chanchani
  • Patent number: 6772513
    Abstract: A method for forming electro-fluidic interconnections in microfluidic devices comprises forming an electrical connection between matching bond pads on a die containing an active electrical element and a microfluidic substrate and forming a fluidic seal ring that circumscribes the active electrical element and a fluidic feedthrough. Preferably, the electrical connection and the seal ring are formed in a single bonding step. The simple method is particularly useful for chemical microanalytical systems wherein a plurality of microanalytical components, such as a chemical preconcentrator, a gas chromatography column, and a surface acoustic wave detector, are fluidically interconnected on a hybrid microfluidic substrate having electrical connection to external support electronics.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: August 10, 2004
    Assignee: Sandia Corporation
    Inventors: Gregory C. Frye-Mason, David Martinez, Ronald P. Manginell, Edwin J. Heller, Rajen Chanchani