Abstract: The disclosed semiconductor device package may include a compute chip configured to perform contextual artificial intelligence and machine perception operations. The disclosed semiconductor device package may additionally include a sensor positioned above the compute chip in the semiconductor device package. The disclosed semiconductor device package may also include one or more electrical connections configured to facilitate communication between the compute chip and the sensor, between the compute chip and a printed circuit board, and between the sensor and the printed circuit board. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed method may include using a wafer-level process to build up a plurality of redistribution layers. The method may additionally include wafer-level mounting a plurality of flip chip die atop the plurality of redistribution layers. The method may also include wafer-level wire bonding the plurality of flip chip die to the plurality of redistribution layers. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Systems and devices describe an augmented-reality glasses having a plurality of panels of light emitters arranged to form an array of light emitters, collimation optics for collimating light received from the array of light emitters, an optical coupler for receiving the collimated light, and a waveguide for display of augmented-reality content to a wearer of the augmented-reality glasses. In some embodiments, the array of light emitters includes light emitters generating three colors, each panel of the plurality of panels of light emitters having light emitters generating a same color, and each panel of the plurality of panels of light emitters positioned on a surface of a semiconductor with at least one integrated circuit. The array of light emitters can be two-dimensional array of light emitters arranged on a common plane and characterized by a pitch that is less than 2 ?m.

Abstract: A method for 3D integration may include forming a first layer of packaging laminate substrate material including a first plurality of vias formed therein. The method may additionally include forming a second layer of packaging laminate substrate material having a second plurality of vias formed therein. The method may also include stacking the first plurality of vias with the second plurality of vias. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method may include mounting a system on chip face down on a fanout package structure in a manner that bonds the system on chip face to face with one or more functional chips included in the fanout package structure. The method may also include mounting an additional functional chip on the system on chip and bonding the additional functional chip to the system on chip. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for three part system on chip memory stacking may include positioning a packaging laminate substrate between a system on chip and a functional chip, wherein the functional chip is connected to the system on chip by a via stack included in the packaging laminate substrate. The method may also include mounting an additional functional chip on the system on chip and bonding the additional functional chip to the system on chip. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Systems and devices describe an augmented-reality glasses having a plurality of panels of light emitters arranged to form an array of light emitters, collimation optics for collimating light received from the array of light emitters, an optical coupler for receiving the collimated light, and a waveguide for display of augmented-reality content to a wearer of the augmented-reality glasses. In some embodiments, the array of light emitters includes light emitters generating three colors, each panel of the plurality of panels of light emitters having light emitters generating a same color, and each panel of the plurality of panels of light emitters positioned on a surface of a semiconductor with at least one integrated circuit. The array of light emitters can be two-dimensional array of light emitters arranged on a common plane and characterized by a pitch that is less than 2 ?m.

Abstract: In some examples, an article comprises a semiconductor including at least one integrated circuit, a ?LED array on a first surface of the semiconductor, and a fill material disposed on a first edge of the semiconductor. The first edge of the ?LED array or the semiconductor is oriented substantially perpendicular to the first surface of the semiconductor.

Abstract: An artificial-reality system including (1) an output device, (2) one or more real-world sensors, and (3) an integrated-circuit package including (A) a general-purpose system-on-chip having a first die-to-die interface and (B) a differentiated artificial-reality task-specific chiplet having a second die-to-die interface coupled to the first die-to-die interface of the general-purpose system-on-chip. The differentiated artificial-reality task-specific chiplet may be configured to generate an output by performing one or more differentiated artificial-reality processing tasks on one or more inputs derived from the one or more real-world sensors, and the general-purpose system-on-chip may be configured to present, via the output device, an artificial reality to a user based at least in part on the output of the differentiated artificial-reality task-specific chiplet. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A multi-chiplet assembly may include a logic chiplet with an active frontside having first active circuitry. A multi-chiplet assembly may include a memory chiplet, electrically coupled to the logic chiplet, with an active frontside having second active circuitry. The active frontside of the logic chiplet may face a first direction, and the active frontside of the memory chiplet may face a second direction opposite the first direction. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A multi-chiplet assembly may include a first logic chiplet. A multi-chiplet assembly may include a memory chiplet electrically coupled to the first logic chiplet. A multi-chiplet assembly may include a second logic chiplet. A multi-chiplet assembly may include a bridging chiplet electrically coupling the first logic chiplet to the second logic chiplet. Various other apparatuses, systems, and methods are also disclosed.

Abstract: Apparatuses include a package substrate with package bonding pads and a die electrically coupled to the package substrate via conductive bonding elements. The die includes a first application-specific integrated circuit (ASIC) with first die input/output pads and a second ASIC with second die input/output pads. Each of the first die input/output pads is electrically coupled to at least one corresponding package bonding pad. At least one of the second die input/output pads is not electrically coupled to any package bonding pad, such that the second ASIC is left in an inoperable state.

Abstract: A circuit assembly may include a first sub-package a first chiplet including an active frontside that includes active circuitry and faces in a first direction, a second sub-package including a second chiplet including an active frontside that includes active circuitry and faces in a second direction opposite the first direction, and a memory sub-package including a memory. The first sub-package, the second sub-package, and the memory sub-package may be arranged so as to overlap each other in the first direction. Various other devices, systems, and methods are also disclosed.

Abstract: A time-of-flight (ToF) module includes a light source, a driver module, and a light sensor. The driver module includes electrical circuitry configured to selectively drive the light source to emit pulsed illumination light. The light sensor is configured to sense returning light reflected from a target. At least one of the light source, driver module, and light sensor is stacked on another to reduce a footprint of the ToF module.

Abstract: Disclosed herein is an LED device that includes a display package and a plurality of LED dies arranged on a top surface of the display package. The display package includes a molding compound, a backplane die, and at least one spacer structure, with the backplane die and the at least one spacer structure being embedded within the molding compound. In some embodiments, the plurality of LED dies includes a first die containing red LEDs, a second die containing green LEDs, and a third die containing blue LEDs. The backplane die includes driver circuits configured to drive LEDs in the plurality of LED dies, for example, LEDs of the first die, the second die, and the third die. The at least one spacer structure has a higher thermal conductivity than the molding compound and is configured to dissipate heat generated by the LEDs in the plurality of LED dies.

Abstract: Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.

Abstract: In some examples, an article comprises a semiconductor including at least one integrated circuit and an inorganic semiconductor layer bonded to a first surface of the semiconductor. The inorganic semiconductor layer comprises a ?LED array, and the first surface of the semiconductor extends beyond a first edge of the inorganic semiconductor layer. The first edge of the inorganic semiconductor layer is oriented substantially perpendicular to the first surface of the semiconductor.

Abstract: Disclosed herein are techniques for aligning a collimator assembly with an array of LEDs and apparatuses formed using the disclosed techniques. According to certain embodiments, a display projector includes a display device and a collimator assembly. The display device includes a backplane including a first plurality of features. The display device further includes a plurality of dies. Each die of the plurality of dies comprises a plurality of light emitting diodes and is bonded to the backplane. The collimator assembly includes a plurality of lenses and a second plurality of features. The collimator assembly is attached to the display device through coupling the first plurality of features with the second plurality of features such that the plurality of dies are aligned with the plurality of lenses.

Abstract: Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.

Abstract: Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.