Patents by Inventor Rajendra D. Pendse

Rajendra D. Pendse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210165318
    Abstract: Disclosed herein are techniques for aligning a collimator assembly with an array of LEDs. According to certain embodiments, a method includes using lithography to form a first plurality of contact pads and a second plurality of contact pads on a backplane; bonding a plurality of dies to the first plurality of contact pads, wherein each of the plurality of dies comprises a plurality of light emitting diodes; forming a first plurality of features on the second plurality of contact pads; and aligning a plurality of lenses on an assembly with the plurality of dies by coupling a second plurality of features on the assembly with the first plurality of features on the second plurality of contact pads.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 3, 2021
    Inventor: Rajendra D. PENDSE
  • Publication number: 20210167268
    Abstract: Disclosed herein are techniques for managing the thermal resistance and the planarity of a display package. According to certain embodiments, a device includes a display package having a molding compound; a plurality of light emitting diode (LED) dies arranged on a top surface of the display package, wherein each LED die of the plurality of LED dies includes a plurality of LEDs; a backplane die embedded within the molding compound of the display package, wherein the backplane die is electrically coupled to each LED die of the plurality of LED dies; and at least one spacer structure embedded within the molding compound of the display package. The backplane die and the at least one spacer structure together provide mechanical support and planar alignment for the plurality of LED dies arranged on the top surface of the display package. The at least one spacer structure has a first thermal conductivity, and the molding compound has a second thermal conductivity lower than the first thermal conductivity.
    Type: Application
    Filed: March 30, 2020
    Publication date: June 3, 2021
    Inventor: Rajendra D. PENDSE
  • Publication number: 20210013099
    Abstract: Disclosed herein are techniques for reducing a variation in the planarity of a display device. In some embodiments, a method includes applying a first pressure to a top surface of a display device at a first temperature. The display device includes a backplane, a plurality of dies, and a plurality of fusible interconnections between the backplane and the plurality of dies. The first pressure is applied in a direction that is perpendicular to a plane of the backplane on which the plurality of dies are arranged. The first pressure and the first temperature are selected to cause the plurality of fusible interconnections to absorb variations in a planarity of the top surface of the display device.
    Type: Application
    Filed: January 15, 2020
    Publication date: January 14, 2021
    Inventor: Rajendra D. PENDSE
  • Publication number: 20200279827
    Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Publication number: 20200266180
    Abstract: An IC chip comprises LED devices exposed on a front side of the IC chip, I/O bumps on a back side of the IC chip, a first die forming a stack with the LED devices and comprising driver circuits electrically connected to the LED devices, a first circuit that extends along the vertical direction from the front side of the IC chip towards a back side of the IC chip and across at least a thickness of the first die to provide electrical connections between the LED devices and at least some of the I/O bumps, a second die including pipelining circuits and control circuits for the driver circuits, a second circuit that extends from the second die, and a circuit board electrically connected to the I/O bumps and to a power system.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 20, 2020
    Inventor: Rajendra D. PENDSE
  • Patent number: 10700041
    Abstract: An assembly of circuit dies is stacked through oxide-oxide bonding. The assembly includes a silicon substrate, in which a plurality of through-silicon-vias are formed. The silicon substrate is attached onto a die through dielectric-dielectric bonding with at least part of the through-silicon-vias electrically connected to the die. The silicon substrate and die are attached onto another die through oxide-oxide bonding. Then the through-silicon-vias are revealed. The silicon substrate functions as a carrier substrate before the revealing. The silicon substrate and two dies can be attached to a printed circuit board, which is electrically connected to the two dies. One or more electrical components can be attached onto the silicon substrate and electrically connected to the die through the through-silicon-vias. The silicon substrate may include a metal element for diffusing heat generated from operation of the one or more electrical components.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 30, 2020
    Assignee: Facebook Technologies, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 10692836
    Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 23, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Publication number: 20200098729
    Abstract: An assembly of circuit dies is stacked through oxide-oxide bonding. The assembly includes a silicon substrate, in which a plurality of through-silicon-vias are formed. The silicon substrate is attached onto a die through dielectric-dielectric bonding with at least part of the through-silicon-vias electrically connected to the die. The silicon substrate and die are attached onto another die through oxide-oxide bonding. Then the through-silicon-vias are revealed. The silicon substrate functions as a carrier substrate before the revealing. The silicon substrate and two dies can be attached to a printed circuit board, which is electrically connected to the two dies. One or more electrical components can be attached onto the silicon substrate and electrically connected to the die through the through-silicon-vias. The silicon substrate may include a metal element for diffusing heat generated from operation of the one or more electrical components.
    Type: Application
    Filed: December 17, 2018
    Publication date: March 26, 2020
    Inventor: Rajendra D. Pendse
  • Patent number: 10580749
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: March 3, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 10388626
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps or interconnect structures formed over an active surface of the die. The bumps can have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. A plurality of conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites under pressure or reflow temperature so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the die and substrate. The masking layer can form a dam to block the encapsulant from extending beyond the semiconductor die. Asperities can be formed over the interconnect sites or bumps.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: August 20, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 10388612
    Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 20, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Byung Joon Han, Rajendra D. Pendse, Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Linda Pei Ee Chua
  • Publication number: 20180096963
    Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.
    Type: Application
    Filed: November 30, 2017
    Publication date: April 5, 2018
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9922915
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. [The fusible portion melts at a temperature which avoids damage to the substrate during reflow.] The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: March 20, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9899286
    Abstract: A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: February 20, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9881894
    Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: January 30, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9865556
    Abstract: A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: January 9, 2018
    Assignee: STATS ChipPAC Pte Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9847309
    Abstract: A semiconductor device has a semiconductor die and substrate with a plurality of stud bumps formed over the semiconductor die or substrate. The stud bumps include a base portion and stem portion extending from the base portion. The stud bumps include a non-fusible material or fusible material. The semiconductor die is mounted to the substrate with the stud bumps electrically connecting the semiconductor die to the substrate. A width of the base portion is greater than a mating conductive trace formed on the substrate. Alternatively, a vertical interconnect structure, such as a conductive column, is formed over the semiconductor die or substrate. The conductive column can have a tapered sidewall or oval cross sectional area. An underfill material is deposited between the semiconductor die and substrate. The semiconductor die includes a flexible property. The vertical interconnect structure includes a flexible property. The substrate includes a flexible property.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: December 19, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Publication number: 20170330840
    Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Byung Joon Han, Rajendra D. Pendse, Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Linda Pei Ee Chua
  • Patent number: 9780057
    Abstract: A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 3, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: RE47600
    Abstract: A semiconductor device has a semiconductor die with a plurality of tapered bumps formed over a surface of the semiconductor die. The tapered bumps can have a non-collapsible portion and collapsible portion. A plurality of conductive traces is formed over a substrate with interconnect sites. A masking layer is formed over the substrate with openings over the conductive traces. The tapered bumps are bonded to the interconnect sites so that the tapered bumps contact the mask layer and conductive traces to form a void within the opening of the mask layer over the substrate. The substrate can be non-wettable to aid with forming the void in the opening of the masking layer. The void provides thermally induced stress relief. Alternatively, the masking layer is sufficiently thin to avoid the tapered interconnect structures contacting the mask layer. An encapsulant or underfill material is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: September 10, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse