Patents by Inventor Rajendra D. Pendse

Rajendra D. Pendse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942589
    Abstract: Disclosed herein is an LED device that includes a display package and a plurality of LED dies arranged on a top surface of the display package. The display package includes a molding compound, a backplane die, and at least one spacer structure, with the backplane die and the at least one spacer structure being embedded within the molding compound. In some embodiments, the plurality of LED dies includes a first die containing red LEDs, a second die containing green LEDs, and a third die containing blue LEDs. The backplane die includes driver circuits configured to drive LEDs in the plurality of LED dies, for example, LEDs of the first die, the second die, and the third die. The at least one spacer structure has a higher thermal conductivity than the molding compound and is configured to dissipate heat generated by the LEDs in the plurality of LED dies.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: March 26, 2024
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 11852835
    Abstract: Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: December 26, 2023
    Assignee: Meta Platforms Technologies, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 11842989
    Abstract: In some examples, an article comprises a semiconductor including at least one integrated circuit and an inorganic semiconductor layer bonded to a first surface of the semiconductor. The inorganic semiconductor layer comprises a ?LED array, and the first surface of the semiconductor extends beyond a first edge of the inorganic semiconductor layer. The first edge of the inorganic semiconductor layer is oriented substantially perpendicular to the first surface of the semiconductor.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: December 12, 2023
    Assignee: Meta Platforms Technologies, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 11668942
    Abstract: Disclosed herein are techniques for aligning a collimator assembly with an array of LEDs and apparatuses formed using the disclosed techniques. According to certain embodiments, a display projector includes a display device and a collimator assembly. The display device includes a backplane including a first plurality of features. The display device further includes a plurality of dies. Each die of the plurality of dies comprises a plurality of light emitting diodes and is bonded to the backplane. The collimator assembly includes a plurality of lenses and a second plurality of features. The collimator assembly is attached to the display device through coupling the first plurality of features with the second plurality of features such that the plurality of dies are aligned with the plurality of lenses.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: June 6, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse
  • Publication number: 20230094261
    Abstract: Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.
    Type: Application
    Filed: December 6, 2022
    Publication date: March 30, 2023
    Inventor: Rajendra D. Pendse
  • Publication number: 20230034214
    Abstract: Disclosed herein are display systems with multiple display packages. In some examples, a first display package includes a first LED die and a first backplane die. The first LED die includes a wire interface that is symmetric about a first plane. The first backplane die includes input/output (I/O) pads that are electrically connected to the wire interface and symmetric about a second plane, perpendicular to the first plane. A similarly configured second display package includes a second LED die with a wire interface identical in layout to that of the first LED die, and a second backplane die with I/O pads identical in layout to that of the first backplane die. The second LED die can be positioned with respect to the second backplane die as a mirror reflection across the second plane of the position of the first LED die with respect to the first backplane die.
    Type: Application
    Filed: October 17, 2022
    Publication date: February 2, 2023
    Inventor: Rajendra D. PENDSE
  • Patent number: 11550158
    Abstract: Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: January 10, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 11545475
    Abstract: An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: January 3, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse
  • Publication number: 20220407987
    Abstract: A camera module includes an image sensor, a lens assembly, a printed circuit board, and a substrate. The image sensor has edges that define a two-dimensional footprint substantially parallel to a surface of the image sensor. The lens assembly is coupled to a top surface of the image sensor and focuses light onto the top surface of the image sensor. Edges of the lens assembly do not extend beyond the footprint. The printed circuit board is below the image sensor and controls the image sensor. The substrate is coupled to a bottom surface of the image sensor and to a top surface of the printed circuit board. The substrate electrically couples the image sensor to the printed circuit board. Edges of the substrate do not extend beyond the footprint.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 22, 2022
    Inventors: Chao Han, Eddie Alex Azuma, Manoj Bikumandla, Rajendra D. Pendse, Cina Hazegh
  • Patent number: 11508700
    Abstract: Disclosed herein are display devices having a left projector and a right projector. According to certain embodiments, a display device includes a first display package having a first LED die, a second LED die, a third LED die, and a first backplane die that is electrically connected to the first LED die, the second LED die, and the third LED die. Each of the first LED die, the second LED die, and the third LED die is symmetric about a first plane that is parallel to an emission direction of the first LED die and perpendicular to a longitudinal direction of the first LED die. The first backplane die is symmetric about a second plane that is parallel to the emission direction of the first LED die and parallel to the longitudinal direction of the first LED die.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: November 22, 2022
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse
  • Publication number: 20220328740
    Abstract: An article including a semiconductor die including integrated circuitry is described. The semiconductor die defines a first major surface, a second major surface opposite the first major surface, and a plurality of perimeter walls joining the first major surface and the second major surface. The article further includes at least one through silicon via extending through the semiconductor die between the first major surface and the second major surface and a fill material surrounding at least part of the semiconductor die. The fill material contacts at least one of the plurality of perimeter walls, and a surface of the fill material is substantially co-planar with the first major surface of the semiconductor die. The article further includes at least one redistribution layer on the first major surface of the semiconductor die and the surface of the fill material.
    Type: Application
    Filed: April 13, 2021
    Publication date: October 13, 2022
    Inventor: Rajendra D. Pendse
  • Publication number: 20220285601
    Abstract: Disclosed herein is an LED device that includes a display package and a plurality of LED dies arranged on a top surface of the display package. The display package includes a molding compound, a backplane die, and at least one spacer structure, with the backplane die and the at least one spacer structure being embedded within the molding compound. In some embodiments, the plurality of LED dies includes a first die containing red LEDs, a second die containing green LEDs, and a third die containing blue LEDs. The backplane die includes driver circuits configured to drive LEDs in the plurality of LED dies, for example, LEDs of the first die, the second die, and the third die. The at least one spacer structure has a higher thermal conductivity than the molding compound and is configured to dissipate heat generated by the LEDs in the plurality of LED dies.
    Type: Application
    Filed: May 12, 2022
    Publication date: September 8, 2022
    Inventor: Rajendra D. PENDSE
  • Publication number: 20220229301
    Abstract: Disclosed herein are techniques for aligning a collimator assembly with an array of LEDs and apparatuses formed using the disclosed techniques. According to certain embodiments, a display projector includes a display device and a collimator assembly. The display device includes a backplane including a first plurality of features. The display device further includes a plurality of dies. Each die of the plurality of dies comprises a plurality of light emitting diodes and is bonded to the backplane. The collimator assembly includes a plurality of lenses and a second plurality of features. The collimator assembly is attached to the display device through coupling the first plurality of features with the second plurality of features such that the plurality of dies are aligned with the plurality of lenses.
    Type: Application
    Filed: March 3, 2022
    Publication date: July 21, 2022
    Inventor: Rajendra D. PENDSE
  • Patent number: 11362251
    Abstract: Disclosed herein are techniques for managing the thermal resistance and the planarity of a display package. According to certain embodiments, a device includes a display package having a molding compound; a plurality of light emitting diode (LED) dies arranged on a top surface of the display package, wherein each LED die of the plurality of LED dies includes a plurality of LEDs; a backplane die embedded within the molding compound of the display package, wherein the backplane die is electrically coupled to each LED die of the plurality of LED dies; and at least one spacer structure embedded within the molding compound of the display package. The backplane die and the at least one spacer structure together provide mechanical support and planar alignment for the plurality of LED dies arranged on the top surface of the display package. The at least one spacer structure has a first thermal conductivity, and the molding compound has a second thermal conductivity lower than the first thermal conductivity.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: June 14, 2022
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 11287656
    Abstract: Disclosed herein are techniques for aligning a collimator assembly with an array of LEDs. According to certain embodiments, a method includes using lithography to form a first plurality of contact pads and a second plurality of contact pads on a backplane; bonding a plurality of dies to the first plurality of contact pads, wherein each of the plurality of dies comprises a plurality of light emitting diodes; forming a first plurality of features on the second plurality of contact pads; and aligning a plurality of lenses on an assembly with the plurality of dies by coupling a second plurality of features on the assembly with the first plurality of features on the second plurality of contact pads.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 29, 2022
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 11251154
    Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: February 15, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Publication number: 20210405382
    Abstract: Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 30, 2021
    Inventor: Rajendra D. Pendse
  • Publication number: 20210335767
    Abstract: An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.
    Type: Application
    Filed: May 12, 2021
    Publication date: October 28, 2021
    Inventor: Rajendra D. PENDSE
  • Publication number: 20210288032
    Abstract: In some examples, an article comprises a semiconductor including at least one integrated circuit and an inorganic semiconductor layer bonded to a first surface of the semiconductor. The inorganic semiconductor layer comprises a ?LED array, and the first surface of the semiconductor extends beyond a first edge of the inorganic semiconductor layer. The first edge of the inorganic semiconductor layer is oriented substantially perpendicular to the first surface of the semiconductor.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 16, 2021
    Inventor: Rajendra D. Pendse
  • Publication number: 20210288036
    Abstract: In some examples, an article comprises a semiconductor including at least one integrated circuit, a ?LED array on a first surface of the semiconductor, and a fill material disposed on a first edge of the semiconductor. The first edge of the ?LED array or the semiconductor is oriented substantially perpendicular to the first surface of the semiconductor.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 16, 2021
    Inventor: Rajendra D. Pendse