Patents by Inventor Rajendra Datar

Rajendra Datar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7162029
    Abstract: A gain or input volume controller and method includes a modified R2R ladder network having a number of R2R branches, switches coupled respectively to the R2R branches, and a switch controller for respectively controlling the switches to control and provide an overall gain value for a signal. The switch controller further includes a mapper for mapping a gain control signal to the switches wherein the gain control signal respectively activates or deactivates the switches. A fine gain control stage provides a fine gain control of the overall gain value. A coarse gain control stage is coupled to the fine gain control stage. The coarse gain control stage includes the modified R2R ladder network and provides a coarse gain control of the overall gain value.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: January 9, 2007
    Assignee: Cirrus Logic, Inc.
    Inventors: Manoj Soman, Krishnan Subramoniam, Hua Hong, Rajendra Datar, John Laurence Melanson
  • Patent number: 7019677
    Abstract: A current steering digital to analog converter includes a current source for selectively providing a selected amount of current to an output in response to input data. The current source includes a selected number of sub-current sources for selectively providing fractions of the selected amount of current to the output. Compensation current sources each provide a selected amount of compensation current to the output. Compensation control circuitry, in response to the input data, selectively activates and de-activates selected ones of the sub-current sources and the compensation current sources to provide current compensation at the output.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: March 28, 2006
    Assignee: Cirrus Logic, Inc.
    Inventors: Manoj Shridhar Soman, Krishnan Subramoniam, Rajendra Datar
  • Patent number: 6850616
    Abstract: A method of detecting frequency errors exceeding a predetermined limit in a sampled signal includes the step of determining a peak amplitude of the signal at a tone frequency for a first frame of samples of the sampled signals using a filter having a first amplitude versus frequency response. A peak amplitude of signal at the tone frequency is determined for a second frame of samples of the sampled signal using a filter having a second amplitude versus frequency response. A ratio between the peak amplitude of the first frame and the peak amplitude of the second frame is calculated and compared against a threshold to detect frequency errors exceeding the predetermined limit. Among other things, this method decouples the frequency error detection problem from the twist factor estimation problem.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: February 1, 2005
    Assignee: Cirrus Logic, Inc.
    Inventors: Manoj Soman, Sachin Ghanekar, Rajendra Datar
  • Publication number: 20040240918
    Abstract: A gain or input volume controller and method includes a modified R2R ladder network having a number of R2R branches, switches coupled respectively to the R2R branches, and a switch controller for respectively controlling the switches to control and provide an overall gain value for a signal. The switch controller further includes a mapper for mapping a gain control signal to the switches wherein the gain control signal respectively activates or deactivates the switches. A fine gain control stage provides a fine gain control of the overall gain value. A coarse gain control stage is coupled to the fine gain control stage. The coarse gain control stage includes the modified R2R ladder network and provides a coarse gain control of the overall gain value.
    Type: Application
    Filed: May 29, 2003
    Publication date: December 2, 2004
    Inventors: Manoj Soman, Krishnan Subramoniam, Hua Hong, Rajendra Datar, John Melanson
  • Patent number: 6642863
    Abstract: A method of performing sample rate conversion in a data converter operating from an oversampling clock corresponding to a native sample rate and a native oversampling factor. A virtual sample rate and a virtual oversampling factor are selected proportional to the native sample rate and the native oversampling factor. A data stream having a data sample rate is sampled by the virtual oversampling factor. The data stream is also resampled with a resampling ratio approximating a ratio of the data sample rate to the virtual sample rate.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: November 4, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Anand Venkitachalam, Dylan Alexander Hester, Brian Frank Bounds, Rajendra Datar, Krishnan Subramoniam
  • Patent number: 6625740
    Abstract: An integrated circuit 300 included a plurality of circuit blocks 202-206 for selectively performing data processing operations in response to a set of instructions. Circuitry 301 dynamically activates and deactivates selected ones of circuit blocks 202-206 during the execution of the set of instructions.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: September 23, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Rajendra Datar, Sachin Ghanekar, Ravindra Gogte, Sebastian Gracias
  • Patent number: 6542094
    Abstract: A sample rate converter for converting a data stream having a first base sampling frequency to a data stream having a second base sampling frequency. Up-sampling circuitry receives first oversampled data having a first oversampling ratio with respects to the first base frequency and outputs second oversampled data having a second oversampling ratio with respects to the first base sampling frequency. Resampling circuitry resamples the second oversampled data by a resampling frequency ratio of integers representing a ratio of the first and second base frequencies and generates third oversampled data having the second oversampling ratio with respects to the second base frequency. Down-sampling circuitry then down-samples the third oversampled data and generates fourth oversampled data having the first oversampling ratio with respects to the second base frequency.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: April 1, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Anad Venkitachalam, Rajendra Datar, Krishnan Subramoniam
  • Patent number: 6489901
    Abstract: A sample rate converter 210, 209 includes a filter 210 for processing digital data in response to a clock controlled by a clock enable signal, the filter 210 receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry 209 generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: December 3, 2002
    Assignee: Cirrus Logic, Inc.
    Inventors: Anand Venkitachalam, Dylan Hester, Joe Welser, Rajendra Datar, Krishnan Subramoniam
  • Publication number: 20020137501
    Abstract: A system 200 for remotely programming a memory 205 includes a host system 201 for developing a set of code. A wireless transmitter 202 is associated with host system 201 for transmitting the code and a wireless receiver 206 is associated with memory 205 for receiving the transmitted code. System 200 further includes circuitry for storing the code received by wireless receiver 206 in memory 205.
    Type: Application
    Filed: March 23, 2001
    Publication date: September 26, 2002
    Inventors: Rajendra Datar, Manoj Soman, Sachin Ghanekar
  • Publication number: 20020097860
    Abstract: A method of detecting frequency errors exceeding a predetermined limit in a sampled signal includes the step of determining a peak amplitude of the signal at a tone frequency for a first frame of samples of the sampled signals using a filter having a first amplitude versus frequency response. A peak amplitude of signal at the tone frequency is determined for a second frame of samples of the sampled signal using a filter having a second amplitude versus frequency response. A ratio between the peak amplitude of the first frame and the peak amplitude of the second frame is calculated and compared against a threshold to detect frequency errors exceeding the predetermined limit. Among other things, this method decouples the frequency error detection problem from the twist factor estimation problem.
    Type: Application
    Filed: January 22, 2001
    Publication date: July 25, 2002
    Applicant: Cirrus Logic, Inc.
    Inventors: Manoj Soman, Sachin Ghanekar, Rajendra Datar
  • Patent number: 6351812
    Abstract: A participant (14) in electronic commerce can validate his/her own certificate (24, 31) by accessing an authority (28, 32) that checks whether the participant's certificate is valid. If the certificate is valid, the authority embeds with the participant's terminal (12) a block of data, in the form of a Cookie (28, 30) that includes a plurality of attributes indicative of the certificate, for example, the certificate's date of expiration. When accessing a secure application (16), the participant presents both the certificate and the authenticating Cookie, obviating the need for a real-time inquiry to the authority, unless the Cookie is stale or missing.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: February 26, 2002
    Assignee: AT&T Corp
    Inventors: Rajendra Datar, Daniel F. Hurley, Vishwa Prasad, Earle H. West
  • Patent number: 6265859
    Abstract: A current mirror 100 includes a current mirroring transistor 103 having a selected aspect ratio for conducting a mirrored current of a selected mirroring ratio with respect to a reference current. A plurality of reference current transistors 201 are disposed in parallel with current mirroring transistor 103, each of the reference current transistors 201 having a current path coupled to a source 105 of the reference current and a selected aspect ratio. A switch 207 is coupled to a control terminal of a selected reference current transistor 201a, for selectively turning on and turning off a selected reference current transistor 201a to adjust the mirroring ratio.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: July 24, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Rajendra Datar, Manoj Soman