Patents by Inventor Rajendra Dias

Rajendra Dias has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10325866
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a bottom surface and a side surface extending from the bottom surface. The side surface can be oriented at a non-perpendicular angle relative to the bottom surface. In another example, an electronic device package can include a top planar surface having a first area, a bottom planar surface having a second area, and a side surface extending between the top surface and the bottom surface. The second area can be larger than the first area. In yet another example, an electronic device package can include a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component. The layer of material can be oriented at an angle of less than 90 degrees relative to the plane.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Eric Li, Joshua Heppner, Rajendra Dias, Mitul Modi
  • Patent number: 10224290
    Abstract: Electromagnetically shielded electronic device technology is disclosed. In an example, a method of making an electronic device package can comprise providing a substrate having a conductor pad and an electronic component. The method can also comprise forming a conformal insulating layer on the substrate and electronic component. The conformal insulating layer conforms to the electronic component. The method can further comprise exposing the conductor pad. In addition, the method can comprise forming an electrically conductive electromagnetic interference (EMI) layer on the insulating layer and in contact with the conductor pad.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Rajendra Dias, Takashi Kumamoto, Yoshishiro Tomita, Mitul Modi, Joshua Heppner, Eric Li
  • Publication number: 20180366421
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a bottom surface and a side surface extending from the bottom surface. The side surface can be oriented at a non-perpendicular angle relative to the bottom surface. In another example, an electronic device package can include a top planar surface having a first area, a bottom planar surface having a second area, and a side surface extending between the top surface and the bottom surface. The second area can be larger than the first area. In yet another example, an electronic device package can include a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component. The layer of material can be oriented at an angle of less than 90 degrees relative to the plane.
    Type: Application
    Filed: December 19, 2017
    Publication date: December 20, 2018
    Applicant: Intel Corporation
    Inventors: Eric Li, Joshua Heppner, Rajendra Dias, Mitul Modi
  • Patent number: 9847304
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a bottom surface and a side surface extending from the bottom surface. The side surface can be oriented at a non-perpendicular angle relative to the bottom surface. In another example, an electronic device package can include a top planar surface having a first area, a bottom planar surface having a second area, and a side surface extending between the top surface and the bottom surface. The second area can be larger than the first area. In yet another example, an electronic device package can include a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component. The layer of material can be oriented at an angle of less than 90 degrees relative to the plane.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Eric Li, Joshua Heppner, Rajendra Dias, Mitul Modi
  • Publication number: 20170186708
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a bottom surface and a side surface extending from the bottom surface. The side surface can be oriented at a non-perpendicular angle relative to the bottom surface. In another example, an electronic device package can include a top planar surface having a first area, a bottom planar surface having a second area, and a side surface extending between the top surface and the bottom surface. The second area can be larger than the first area. In yet another example, an electronic device package can include a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component. The layer of material can be oriented at an angle of less than 90 degrees relative to the plane.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Applicant: Intel Corporation
    Inventors: Eric Li, Joshua Heppner, Rajendra Dias, Mitul Modi
  • Publication number: 20170186697
    Abstract: Electromagnetically shielded electronic device technology is disclosed. In an example, a method of making an electronic device package can comprise providing a substrate having a conductor pad and an electronic component. The method can also comprise forming a conformal insulating layer on the substrate and electronic component. The conformal insulating layer conforms to the electronic component. The method can further comprise exposing the conductor pad. In addition, the method can comprise forming an electrically conductive electromagnetic interference (EMI) layer on the insulating layer and in contact with the conductor pad.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Applicant: Intel Corporation
    Inventors: Rajendra Dias, Takashi Kumamoto, Yoshishiro Tomita, Mitul Modi, Joshua Heppner, Eric Li
  • Publication number: 20080272481
    Abstract: An electrically conductive pin comprising a pin stem and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head defines at least one slot therein, the at least one slot being configured to allow gases to escape therethrough from a region at an underside of the pin head.
    Type: Application
    Filed: May 4, 2007
    Publication date: November 6, 2008
    Inventors: Rajendra Dias, Xinyan Zhao
  • Patent number: 7280190
    Abstract: Apparatuses, methods, and systems associated with and/or having components capable of, isolating defects in microelectronic packages are disclosed herein. In various embodiments, a defect-isolation apparatus may include an optoelectronic module to convert an optical test signal to an electrical test signal and provide the electrical test signal to a device under test; an electro-optic probe including an electro-optic crystal to polarize an optical sampling signal upon application of an electrical test signal reflected from the device under test to the electro-optic crystal; and an output module configured to receive the polarized optical sampling signal, and produce an electrical output signal as a function of time based at least in part on the polarized optical sampling signal, the electrical output signal adapted to facilitate isolation of the location(s) of the defect(s) in the device under test.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Zhiyong Wang, Rajendra Dias, Deepak Goyal