Abstract: An apparatus and method is described of reducing joint weight for integers involved in a scalar multiplication, such as during cryptography. By way of example, the method is utilized within elliptic curve cryptography (ECC), wherein reducing joint weight speeds the execution of the scalar multiplication and reduces memory overhead. Generally, the recoding technique of the present invention involves generating a binary signed-digit representation for the two or more non-negative integers and then replacing groups of the binary signed-digits from left to right according to a predetermined pattern in order to reduce joint weight. The recoding process of the present invention is performed in a left-to-right order which is compatible with the order of the scalar multiplication. The present method reduces the amount of memory required for performing cryptography and allows it to be implemented in hardware or any desired combination of hardware and software.

Abstract: The present invention provides an apparatus and method for implementing low-power linear feedback shift registers (LFSR) that efficiently produce single or multiple outputs. In one case of single output generation the gates are permanently connected to the respective flip-flops reducing the number of switches necessary. In the case of multiple outputs the outputs are generated several clock cycles at once, which enables the frequency of operation to be reduced by a factor equal to the number of outputs produced at a time. In either case grouping is utilized for reducing the number of gates necessary and the power dissipation. The invention is applicable to a wide range of applications, including but not limited to data compression, encryption, communication, error correction, built-in self-test, and so forth.