Abstract: A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.

Abstract: Embodiments herein describe assigning integrated circuits with defects as variants of the integrated circuit design. Each variant can deactivate different circuitry in the integrated circuit design. A location of the defect can be matched to a variant that has a deactivated region that covers the defect. The integrated circuit can then be assigned to that variant.

Abstract: Methods and systems herein can include a processor configured to obtain a set of images that shows a user's head and a reference object, generate a user's head model of the user's head based at least in part on the set of images, and generate a reference object model of the reference object based at least in part on the set of images. The processor can further be configured to determine an orientation and a size of the reference object model based at least in part on a relative location of the reference object relative to the user's head in the set of images and use the reference object model, the orientation of the reference object model, the size of the reference object, and a known dimension of the reference object to determine scaling information. The processor can then be configured to apply the scaling information to the user's head model to obtain a scaled user's head model. The system can also include a memory coupled to the processor and configured to provide the processor with instructions.

Abstract: The present disclosure is related to methods, systems, and machine-readable media for unattended snapshot reversion for upgrades. A request to upgrade a virtual computing instance (VCI) in a software-defined datacenter (SDDC) can be received. A snapshot of the VCI can be created, wherein the snapshot excludes a predefined storage partition associated with the VCI. An upgrade of the VCI can be executed. Executing the upgrade can include performing a plurality of upgrade steps and storing, in the partition, information pertaining to the execution of the upgrade. The snapshot can be reverted to responsive to a cancellation of the upgrade. The upgrade of the VCI can be re-executed from the snapshot. Re-executing the upgrade can include performing a different plurality of upgrade steps determined based on the information pertaining to the execution of the upgrade.

Abstract: A method comprising: calculating a velocity threshold for an entity, the entity including an individual worker or a team of workers; calculating a velocity for the entity by classifying a first signature corresponding to the entity with a first machine learning (M/L) classifier, the velocity being a metric that measures a current productivity of the entity; detecting whether the velocity meets the velocity threshold; and outputting an alert when the velocity meets the velocity threshold.

Abstract: A system and method for scaling a user's head based on estimated facial features are disclosed. In an example, a system includes a processor configured to obtain a set of images of a user's head; generate a model of the user's head based on the set of images; determine a scaling ratio based on the model of the user's head and estimated facial features; and apply the scaling ratio to the model of the user's head to obtain a scaled user's head model; and a memory coupled to the processor and configured to provide the processor with instructions.

Abstract: A method for use in a hosting system of a retail website, comprising: receiving respective first values for a plurality of parameters of an auto-buy campaign, the respective first values being specified by an administrator of the retail website hosting system; calculating a configuration score for the auto-buy campaign based on the respective first values for the plurality of parameters of the auto-buy campaign, the configuration score being indicative of a percentage of auto-buy bids submitted as part of the auto-buy campaign that are expected to result in a purchase; and outputting an indication of the configuration score for presentation to the administrator.

Abstract: Methods and systems herein can include a processor configured to obtain a set of images that shows a user's head and a reference object, generate a user's head model of the user's head based at least in part on the set of images, and generate a reference object model of the reference object based at least in part on the set of images. The processor can further be configured to determine an orientation and a size of the reference object model based at least in part on a relative location of the reference object relative to the user's head in the set of images and use the reference object model, the orientation of the reference object model, the size of the reference object, and a known dimension of the reference object to determine scaling information. The processor can then be configured to apply the scaling information to the user's head model to obtain a scaled user's head model. The system can also include a memory coupled to the processor and configured to provide the processor with instructions.

Abstract: This invention pertains to a gluten-free bakery product which comprises a flour/starch component comprising a heat moisture treated flour. Such bakery products more closely mimic the conventional, wheat flour containing products than other gluten-free products.

Abstract: This invention pertains to a gluten-free bakery product which comprises a flour/starch component comprising a heat moisture treated flour. Such bakery products more closely mimic the conventional, wheat flour containing products than other gluten-free products.

Abstract: Separate executable agents each perform tasks on associated information that is changing over time, to produce current information, Inputs and outputs are delivered among agents to enable assembly of a body of aggregated and summarized management information, based on the current information, to be used to manage at least a portion of an enterprise.

Abstract: A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially faster than that of the master tester. The master tester instructs the TLA to monitor data that the DUT receives from the slave tester to detect a predetermined data pattern within the data. The slave tester transmits data including the predetermined data pattern to the DUT. The DUT receives the data. When the TLA in the DUT detects the predetermined data pattern in the received data, the TLA stores that data pattern as a stored data pattern. The master tester retrieves the stored data pattern and compares the stored data pattern with the original predetermined data pattern. If the master tester determines that the stored data pattern is the same as the original predetermined data pattern, then the master tester generates a pass result.

Abstract: A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially faster than that of the master tester. The master tester instructs the TLA to monitor data that the DUT receives from the slave tester to detect a predetermined data pattern within the data. The slave tester transmits data including the predetermined data pattern to the DUT. The DUT receives the data. When the TLA in the DUT detects the predetermined data pattern in the received data, the TLA stores that data pattern as a stored data pattern. The master tester retrieves the stored data pattern and compares the stored data pattern with the original predetermined data pattern. If the master tester determines that the stored data pattern is the same as the original predetermined data pattern, then the master tester generates a pass result.

Abstract: Separate executable agents each perform tasks on associated information that is changing over time, to produce current information, Inputs and outputs are delivered among agents to enable assembly of a body of aggregated and summarized management information, based on the current information, to be used to manage at least a portion of an enterprise.

Abstract: A frozen dough comprising flour, a high yeast level comprising one or more yeast with activity covering temperature range of 33-140° F., emulsifiers, dough conditioners, stabilizers, sugar, lipid source and optionally supplemental gluten such that the frozen dough does not require a conventional proofing (proofer) step prior to freezing or prior to baking. When the frozen dough is thawed in a retarder at 33-42° F. for at least 12 hours, or at an elevated temperature of between 43-85° F. for at least 1 hour, and then baked, the baked products have good appearance, taste and texture, and a specific volume of at least 4 cc/gram.

Abstract: In one form of the invention, an apparatus has a first switch operable in an error injection state for interrupting a transfer of first data from a memory device to a test system, and in a normal state for permitting unimpeded data transfer. The apparatus has a second switch operable in an error injection state for sending second data to the test system instead of corresponding bits of the first data. Logic circuitry of the apparatus reads the first data and controls an error injection sequence that includes switching the first and second switches from their respective normal states to their respective error injection states responsive to receiving the command. The apparatus determines whether at least one of the corresponding data bits of the first and second data have disparate logic states independently of switching the first and second switches back to their respective normal states.