Patents by Inventor Rajendra Narasimhan

Rajendra Narasimhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-level circuit structure
    Publication number: 20020048944
    Abstract: In a semiconductor device, a conductive structure comprising an interconnect and an overlying plug integrally extending therefrom is provided. The structure can be provided by a damascene process, wherein an opening is defined in insulation deep enough to accommodate the height of an interconnect and its overlying plug. The opening is filled with metal, and non-plug areas of the metal are then recessed down to a standard interconnect height within the trench. The full height of the metal is retained at the plug site. Oxide is then deposited over the recessed portions. Alternatively, a continuous metal layer is provided that is deep enough to accommodate the height of an interconnect and its overlying plug. The metal is then etched to form the interconnect/plug structure, and insulation is deposited thereover. Multiple structures may be provided at the same level using these processes, and multiple levels of these structures may be similarly provided.
    Type: Application
    Filed: November 9, 2001
    Publication date: April 25, 2002
    Inventors: Sanh D. Tang, Rajendra Narasimhan
  • Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench
    Patent number: 6352916
    Abstract: In a semiconductor device, a conductive structure comprising an interconnect and an overlying plug integrally extending therefrom is provided. The structure can be provided by a damascene process, wherein an opening is defined in insulation deep enough to accommodate the height of an interconnect and its overlying plug. The opening is filled with metal, and non-plug areas of the metal are then recessed down to a standard interconnect height within the trench. The full height of the metal is retained at the plug site. Oxide is then deposited over the recessed portions. Alternatively, a continuous metal layer is provided that is deep enough to accommodate the height of an interconnect and its overlying plug. The metal is then etched to form the interconnect/plug structure, and insulation is deposited thereover. Multiple structures may be provided at the same level using these processes, and multiple levels of these structures may be similarly provided.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: March 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Rajendra Narasimhan