Patents by Inventor Rajendra Prasad Mishra

Rajendra Prasad Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11816027
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request for garbage collection, identify a range of physical blocks in a storage device, query a bitmap, the bitmap having a bit for each physical block in the range of physical blocks, determine a status associated with a first bit from the bitmap, in response to determining the status associated with the first bit is a first state, add a first physical block associated with the first bit to a list of physical blocks for relocation, and relocate the list of physical blocks.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: November 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Publication number: 20220121564
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request for garbage collection, identify a range of physical blocks in a storage device, query a bitmap, the bitmap having a bit for each physical block in the range of physical blocks, determine a status associated with a first bit from the bitmap, in response to determining the status associated with the first bit is a first state, add a first physical block associated with the first bit to a list of physical blocks for relocation, and relocate the list of physical blocks.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 21, 2022
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Patent number: 11216361
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request for garbage collection, identify a range of physical blocks in a storage device, query a bitmap, the bitmap having a bit for each physical block in the range of physical blocks, determine a status associated with a first bit from the bitmap, in response to determining the status associated with the first bit is a first state, add a first physical block associated with the first bit to a list of physical blocks for relocation, and relocate the list of physical blocks.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 4, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Patent number: 10725669
    Abstract: A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive in a memory, a first logical block entry for a first dump group and a second logical block entry for a second dump group; store in a reverse translation table, the first logical block entry for the first dump group and the second logical block entry for the second dump group; determine a first sequence number associated with the stored first logical block entry and the stored second logical block entry in the reverse translation table, wherein the first sequence number is a snapshot marker that determines a timestamp associated with the first logical block and the second logical block; and persist the first logical block entry for the first dump group in the storage device.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: July 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Patent number: 10235287
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request to select translation table entries to store in a storage device, determine a plurality of translation table entries associated with a dump unit, allocate the plurality of translation table entries into a first group of translation table entries associated with a first node and a second group of translation table entries associated with a second node, the first group of translation table entries being frequently accessed and the second group of translation table entries being rarely accessed. determine a first status associated with a first recent access bit for a first translation table entry, the first translation table entry being included in the first group of translation table entries, and add the first translation table entry to the second group of translation table entries.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 19, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Patent number: 10175896
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to identify a plurality of dump units associated with a translation table in a storage device, determine a plurality of snapshot markers associated with the plurality of dump units, calculate a first value of a first snapshot marker from the plurality of snapshot markers in the storage device, identify a second snapshot marker from an additional source, the second snapshot marker having a second value satisfying the first value, retrieve a dump unit associated with the second snapshot marker from the additional source, and reconstruct the translation table using the dump unit.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 8, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Publication number: 20180329637
    Abstract: A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive in a memory, a first logical block entry for a first dump group and a second logical block entry for a second dump group; store in a reverse translation table, the first logical block entry for the first dump group and the second logical block entry for the second dump group; determine a first sequence number associated with the stored first logical block entry and the stored second logical block entry in the reverse translation table, wherein the first sequence number is a snapshot marker that determines a timestamp associated with the first logical block and the second logical block; and persist the first logical block entry for the first dump group in the storage device.
    Type: Application
    Filed: July 20, 2018
    Publication date: November 15, 2018
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Patent number: 10108340
    Abstract: Embodiments of the present invention receive I/O commands expressed in either vendor-specific or non-vendor-specific protocols and normalize them into a common format for execution by different memory devices. Embodiments of the present invention identify these I/O commands using parameters common to both types of protocols. In this fashion, embodiments store normalized commands in data structures for execution by memory devices in which the normalized commands represent instructions for performing an action corresponding with execution of the original I/O command. Accordingly, embodiments of the present invention save resources with respect to hardware and software maintenance costs.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: October 23, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sriram Rupanagunta, Ashish Singhai, Sandeep Sharma, Srikant Sadasivam, Krishanth Skandakumaran, George Moussa, Rajendra Prasad Mishra, Kenneth Alan Okin
  • Patent number: 10031680
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to identify a plurality of dump units associated with a translation table in a storage device, determine a plurality of snapshot markers associated with the plurality of dump units, calculate a first value of a first snapshot marker from the plurality of snapshot markers in the storage device, identify a second snapshot marker from an additional source, the second snapshot marker having a second value satisfying the first value, retrieve a dump unit associated with the second snapshot marker from the additional source, and reconstruct the translation table using the dump unit.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 24, 2018
    Assignee: HGST Netherlands B.V.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Patent number: 9886196
    Abstract: Embodiments of the present invention are operable to efficiently schedule memory device commands, such as flash memory device commands, while taking into account the interdependencies of processing such commands. As such embodiments of the present invention order commands to make sure that data is written and read from memory devices in a coherent fashion using command groups. Commands within such command groups are scheduled concurrently or in parallel. In this fashion, embodiments of the present invention promote efficient execution of memory device commands while maintaining any required arbitrary ordering requirements.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: February 6, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sriram Rupanagunta, Ashish Singhai, Sandeep Sharma, Srikant Sadasivam, Krishanth Skandakumaran, George Moussa, Rajendra Prasad Mishra, Kenneth Alan Okin
  • Publication number: 20180004652
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request for garbage collection, identify a range of physical blocks in a storage device, query a bitmap, the bitmap having a bit for each physical block in the range of physical blocks, determine a status associated with a first bit from the bitmap, in response to determining the status associated with the first bit is a first state, add a first physical block associated with the first bit to a list of physical blocks for relocation, and relocate the list of physical blocks.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Publication number: 20180004656
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request to select translation table entries to store in a storage device, determine a plurality of translation table entries associated with a dump unit, allocate the plurality of translation table entries into a first group of translation table entries associated with a first node and a second group of translation table entries associated with a second node, the first group of translation table entries being frequently accessed and the second group of translation table entries being rarely accessed. determine a first status associated with a first recent access bit for a first translation table entry, the first translation table entry being included in the first group of translation table entries, and add the first translation table entry to the second group of translation table entries.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Publication number: 20180004437
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to identify a plurality of dump units associated with a translation table in a storage device, determine a plurality of snapshot markers associated with the plurality of dump units, calculate a first value of a first snapshot marker from the plurality of snapshot markers in the storage device, identify a second snapshot marker from an additional source, the second snapshot marker having a second value satisfying the first value, retrieve a dump unit associated with the second snapshot marker from the additional source, and reconstruct the translation table using the dump unit.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Patent number: 9811285
    Abstract: Data is stored as a first collection of memory blocks distributed across a first set of memory devices. It is determined that a first memory device in the first set is in a degraded state. Data is recovered corresponding to a first memory block in the first collection of memory blocks that is stored in the first memory device, which is configured to include a first number of memory blocks. The recovered data is stored in a second memory device as a new memory block, which is added to the first collection of memory blocks. The first memory device is removed from the first set and reconfigured with a second number of memory blocks that is less than the first number of memory blocks. Memory blocks in a second collection of memory blocks distributed across a second set of memory devices is stored in the reconfigured first memory device.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 7, 2017
    Assignee: VIRIDENT SYSTEMS, LLC
    Inventors: Vijay Karamcheti, Swamy Gowda, Rajendra Prasad Mishra, Shibabrata Mondal
  • Publication number: 20170115887
    Abstract: Embodiments of the present invention are operable to efficiently schedule memory device commands, such as flash memory device commands, while taking into account the interdependencies of processing such commands. As such embodiments of the present invention order commands to make sure that data is written and read from memory devices in a coherent fashion using command groups. Commands within such command groups are scheduled concurrently or in parallel. In this fashion, embodiments of the present invention promote efficient execution of memory device commands while maintaining any required arbitrary ordering requirements.
    Type: Application
    Filed: January 11, 2016
    Publication date: April 27, 2017
    Inventors: Sriram RUPANAGUNTA, Ashish SINGHAI, Sandeep SHARMA, Srikant SADASIVAM, Krishanth SKANDAKUMARAN, George MOUSSA, Rajendra Prasad MISHRA, Kenneth Alan Okin
  • Publication number: 20170115888
    Abstract: Embodiments of the present invention receive I/O commands, expressed in either vendor-specific or non-vendor-specific protocols and normalize them into a common format for execution by different memory devices. Embodiments of the present invention identify these I/O commands using parameters common to both types of protocols. In this fashion, embodiments store normalized commands in data structures for execution by memory devices in which the normalized, commands represent instructions for performing an action corresponding with execution of the original I/O command. Accordingly, embodiments of the present invention save resources with respect to hardware and software maintenance costs.
    Type: Application
    Filed: January 11, 2016
    Publication date: April 27, 2017
    Inventors: Sriram Rupanagunta, Ashish Singhai, Sandeep Sharma, Srikant Sadasivam, Krishanth Skandakumaran, George Moussa, Rajendra Prasad Mishra, Kenneth Alan Okin
  • Patent number: 9286002
    Abstract: Data is stored as a first collection of memory blocks distributed across a first set of memory devices. It is determined that a first memory device in the first set is in a degraded state. Data is recovered corresponding to a first memory block in the first collection of memory blocks that is stored in the first memory device, which is configured to include a first number of memory blocks. The recovered data is stored in a second memory device as a new memory block, which is added to the first collection of memory blocks. The first memory device is removed from the first set and reconfigured with a second number of memory blocks that is less than the first number of memory blocks. Memory blocks in a second collection of memory blocks distributed across a second set of memory devices is stored in the reconfigured first memory device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 15, 2016
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Swamy Gowda, Rajendra Prasad Mishra, Shibabrata Mondal