Patents by Inventor Rajendra S. Yavatkar

Rajendra S. Yavatkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11829789
    Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Ashok Sunder Rajan, Richard A. Uhlig, Rajendra S. Yavatkar, Tsung-Yuan C. Tai, Christian Maciocco, Jeffrey R. Jackson, Daniel J. Dahle
  • Publication number: 20220171643
    Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
    Type: Application
    Filed: February 14, 2022
    Publication date: June 2, 2022
    Applicant: Intel Corporation
    Inventors: Ashok Sunder Rajan, Richard A. Uhlig, Rajendra S. Yavatkar, Tsung-Yuan C. Tai, Christian Maciocco, Jeffrey R. Jackson, Daniel J. Dahle
  • Patent number: 11301275
    Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Ashok Sunder Rajan, Richard A. Uhlig, Rajendra S. Yavatkar, Tsung-Yuan C. Tai, Christian Maciocco, Jeffrey R. Jackson, Daniel J. Dahle
  • Publication number: 20200174811
    Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
    Type: Application
    Filed: February 10, 2020
    Publication date: June 4, 2020
    Applicant: Intel Corporation
    Inventors: Ashok Sunder Rajan, Richard A. Uhlig, Rajendra S. Yavatkar, Tsung-Yuan C. Tai, Christian Maciocco, Jeffrey R. Jackson, Daniel J. Dahle
  • Patent number: 10558481
    Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: February 11, 2020
    Assignee: INTEL CORPORATION
    Inventors: Ashok Sunder Rajan, Richard A. Uhlig, Rajendra S. Yavatkar, Tsung-Yuan C. Tai, Christian Maciocco, Jeffrey R. Jackson, Daniel J. Dahle
  • Publication number: 20180225136
    Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
    Type: Application
    Filed: November 14, 2017
    Publication date: August 9, 2018
    Applicant: INTEL CORPORATION
    Inventors: Ashok Sunder Rajan, Richard A. Uhlig, Rajendra S. Yavatkar, Tsung-Yuan C. Tai, Christian Maciocco, Jeffrey R. Jackson, Daniel J. Dahle
  • Patent number: 9817684
    Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: November 14, 2017
    Assignee: INTEL CORPORATION
    Inventors: Ashok Sunder Rajan, Richard A. Uhlig, Rajendra S. Yavatkar, Tsung-Yuan C. Tai, Christian Maciocco, Jeffrey R. Jackson, Daniel J. Dahle
  • Patent number: 9632895
    Abstract: A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 25, 2017
    Assignee: INTEL CORPORATION
    Inventors: Sankaran M Menon, Rajendra S Yavatkar, Eyal Dolev, Sridhar Valluru, Ramana Rachakonda
  • Patent number: 9390031
    Abstract: Apparatuses and methods for page coloring to associate memory pages with programs are disclosed. In one embodiment, an apparatus includes a paging unit and an interface to access a memory. The paging unit includes translation logic and comparison logic. The translation logic is to translate a first address to a second address. The first address is to be provided by an instruction stored in a first page in the memory. The translation is based on an entry in a data structure, and the entry is to include a base address of a second page in the memory including the second address. The comparison logic is to compare the color of the first page to the color of the second page. The color of the first page is to indicate association of the first page with a first program including the first instruction. The data structure entry is also to include the color of the second page to indicate association of the second page with the first program or a second program.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: David M. Durham, Ravi L. Sahita, Dylan C. Larson, Rajendra S. Yavatkar
  • Publication number: 20140310707
    Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
    Type: Application
    Filed: October 16, 2013
    Publication date: October 16, 2014
    Inventors: Ashok Sunder Rajan, Richard A. Uhlig, Rajendra S. Yavatkar, Tsung-Yuan C. Tai, Christian Maciocco, Jeffrey R. Jackson, Daniel J. Dahle
  • Publication number: 20130339790
    Abstract: A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data.
    Type: Application
    Filed: March 15, 2013
    Publication date: December 19, 2013
    Inventors: Sankaran M. Menon, Rajendra S. Yavatkar, Eyal Dolev, Sridhar Valluru, Ramana Rachakonda
  • Patent number: 8553693
    Abstract: An embodiment may include network controller to be comprised in a first node. The node may be communicatively coupled to a network and may include a host processor to execute an operating system environment. The operating system environment may include, at least in part, a communication protocol stack and an application. The circuitry may receive, at least in part, a packet from the network. The packet may include, at least in part, a header and payload. At least one portion of the payload may be associated with the application. The circuitry may issue at least one portion of the header to the stack. The circuitry may issue the at least one portion of the payload to a destination device in a manner that by-passes involvement of the stack. The destination device may be specified, at least in part, by the application. Many alternatives, variations, and modifications are possible.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: October 8, 2013
    Assignee: Intel Corporation
    Inventors: Ren Wang, Tsung-Yuan C. Tai, Christian Maciocco, Rajendra S. Yavatkar, Lakshman Krishnamurthy, Michael J. Espig
  • Patent number: 8085765
    Abstract: A border gateway has a control card and at least one line card. The control card has a control processor to execute a control portion of an exterior gateway protocol and a routing table of exterior gateway routes and devices. The line card has a line processor to execute an offload portion of an exterior gateway protocol and a communications port to allow termination of at least one communication link. A backplane allows the control card and the line card to communicate.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: December 27, 2011
    Assignee: Intel Corporation
    Inventors: Sanjay Bakshi, Rajendra S. Yavatkar
  • Publication number: 20110222537
    Abstract: An embodiment may include network controller to be comprised in a first node. The node may be communicatively coupled to a network and may include a host processor to execute an operating system environment. The operating system environment may include, at least in part, a communication protocol stack and an application. The circuitry may receive, at least in part, a packet from the network. The packet may include, at least in part, a header and payload. At least one portion of the payload may be associated with the application. The circuitry may issue at least one portion of the header to the stack. The circuitry may issue the at least one portion of the payload to a destination device in a manner that by-passes involvement of the stack. The destination device may be specified, at least in part, by the application. Many alternatives, variations, and modifications are possible.
    Type: Application
    Filed: March 10, 2010
    Publication date: September 15, 2011
    Inventors: Ren Wang, Tsung-Yuan C. Tai, Christian Maciocco, Rajendra S. Yavatkar, Lakshman Krishnamurthy, Michael J. Espig
  • Patent number: 7380168
    Abstract: According to some embodiments, execution information is received from a first development tool. Execution information is also received from a second development tool. Based on the first execution information and the second execution information, operation of the first development tool may be controlled. According to some embodiments, the first and second development tools are associated with different processor architectures.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventors: Makaram Raghunandan, Rajendra S. Yavatkar, Shou C. Chen, Dave Edwards, Geoffrey R. Gustafson
  • Patent number: 7177323
    Abstract: A multi-media call application is disclosed. The application guarantees quality of service (QOS) for a packet based multi-media call (CALL). The guaranty is effectuated through call associated individual media stream bandwidth control.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Rajendra S. Yavatkar, James E. Toga
  • Patent number: 6973488
    Abstract: Policy information is distributed to remote network devices by mapping high-level policy information into low-level configuration information and distributing the low-level configuration information to the remote network devices.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: December 6, 2005
    Assignee: Intel Corporation
    Inventors: Rajendra S. Yavatkar, David M. Durham, Russell J. Fenger
  • Patent number: 6804717
    Abstract: Providing quality of service includes reserving resources to transmit data from a source location to a destination location and transmitting the data from the source location to the destination location using the reserved resources and based on characteristics of the data and of the destination location.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: October 12, 2004
    Assignee: Intel Corporation
    Inventors: Sanjay Bakshi, Rajendra S. Yavatkar
  • Publication number: 20040136371
    Abstract: A router uses a distributed implementation of a routing control protocol to route a packet between a plurality of computer networks. The router includes a control-plane having a control-plane processor to implement a central control portion of the control protocol and a plurality of forwarding-planes, each having a forwarding-plane processor, to implement an offload control portion of the control protocol. A back-plane connects the forwarding-planes to each other and to the control-plane. Together, these components route a packet based on the distributed implementation of the control protocol. The protocol may be a signaling protocol, such as RSVP-TE, or a routing protocol, such as OSPF.
    Type: Application
    Filed: November 13, 2003
    Publication date: July 15, 2004
    Inventors: Rajeev D. Muralidhar, Sanjay Bakshi, Rajendra S. Yavatkar, Suhail Ahmed
  • Patent number: 6601082
    Abstract: A system and method for managing a network using a policy tree which includes a plurality of levels (e.g., two levels, five levels, etc.) is described. When the network receives a request to provide an action to a particular source, the network determines if the action is available as a function of at least one level of the plurality of levels. If the action is available, the network determines if the particular source is authorized to be provided with the action as a function of at least one rule of at least one further level of the plurality of levels. If the particular source is authorized, the network provides the action to the particular source.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: July 29, 2003
    Assignee: Intel Corporation
    Inventors: David M. Durham, Russell J. Fenger, Rajendra S. Yavatkar