Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.

Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodetector and methods of manufacture. The structure includes: a photodetector; and a semiconductor material on the photodetector, the semiconductor material comprising a first dopant type, a second dopant type and intrinsic semiconductor material separating the first dopant type from the second dopant type.

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

Abstract: A transistor is provided. The transistor includes a substrate, a gate structure, a semiconductor structure, and a dielectric component. The gate structure is over the substrate and the semiconductor structure is adjacent to the gate structure. The semiconductor structure has a first side facing the gate structure and a second side laterally opposite the first side. The dielectric component is in the substrate. The dielectric component has a first portion adjacent to the second side of the semiconductor structure and a second portion under the first portion, wherein the second portion extends under the gate structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-electron-mobility transistors and methods of manufacture. A structure includes: a semiconductor layer on a semiconductor material; a gate structure on the semiconductor layer; a drain region comprising the semiconductor layer and which is adjacent to the gate structure; an ohmic contact which includes at least one terminal connection connecting to the semiconductor material, the ohmic contact being adjacent to the drain region and spaced away from the gate structure; and a capacitance reducing structure adjacent to the drain region.

Abstract: Semiconductor device structures with device isolation and methods of forming a semiconductor device structure with device isolation. The structure comprises a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer in a cavity in the first semiconductor layer, and a device structure including a doped region in the second semiconductor layer. The first semiconductor layer comprises a porous semiconductor material, and the second semiconductor layer comprises a single-crystal semiconductor material.

Abstract: Embodiments of the disclosure provide a circuit structure including an electrically programmable fuse (efuse) and lateral bipolar transistor. A structure of the disclosure includes a lateral bipolar transistor within a semiconductor layer and over a substrate. An insulator layer is over a portion of the semiconductor layer. An efuse structure is within a polycrystalline semiconductor layer and over the insulator layer. The efuse structure is over a current path through the lateral bipolar transistor.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors and methods of manufacture. The structure includes: a trench structure in a semiconductor substrate; at least one fin structure comprising semiconductor material which extends from a bottom of the trench structure; a photodetector material within the trench structure and extends from the at least one fin structure; a first contact connected to and on a first side of the photodetector material; and a second contact connected to the semiconductor substrate on a second side of the photodetector material.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

Abstract: A photodetector structure includes a first semiconductor material layer over a doped well in a substrate. The photodetector structure includes an air gap vertically between the first semiconductor material layer and a first portion of the doped well. The photodetector structure includes an insulative collar on the first portion of the doped well and laterally surrounding the air gap. The photodetector structure may include a second semiconductor material layer on the first portion of the doped well and laterally surrounded by the insulative collar. The photodetector structure may include a third semiconductor layer over the first semiconductor layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to laterally-diffused metal-oxide semiconductors and methods of manufacture. The structure includes: a drift region within a semiconductor substrate; a shallow trench isolation structure extending within the drift region; and a gate structure over the semiconductor substrate and extending within the shallow trench isolation structure.

Abstract: Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor layer, a device layer, and heat dissipating structures. The semiconductor layer is over the substrate and the device layer is over the semiconductor layer. The device layer includes a first ohmic contact and a second ohmic contact. The heat dissipating structures are at least through the substrate and the semiconductor layer, and between the first ohmic contact and the second ohmic contact.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodetector and methods of manufacture. The structure includes: a photodetector; and a semiconductor material on the photodetector, the semiconductor material comprising a first dopant type, a second dopant type and intrinsic semiconductor material separating the first dopant type from the second dopant type.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge device (ESD) with a pinch resistor and methods of manufacture. The structure includes: a semiconductor substrate; a shallow trench isolation structure extending into the semiconductor substrate; an amorphous layer in the semiconductor substrate and below the shallow trench isolation structure; and a pinch resistor between the shallow trench isolation structure and the amorphous layer.

Abstract: Disclosed are a structure and method. The structure includes a substrate having monocrystalline lower and upper portions and a high resistance portion (e.g., a trap-rich amorphous portion) between the lower and upper portions. An isolation region extends through the upper portion, is above the high resistance portion, and is positioned laterally adjacent to a device section of the upper portion also above the high resistance portion. One or more devices (e.g., a diode, multiple diodes, a diode string, multiple diode strings, etc.) are on the trench isolation region, on the device section, and/or within the device section. The device(s) are separated from the lower portion by the high resistance portion and, potentially, by the isolation region or the device section. Such device(s) can be employed for electrostatic discharge (ESD) protection on RFIC chips and can sustain a larger RF voltage, provide area savings, reduce parasitic capacitance, improve harmonics, etc.

Abstract: Device structures with an isolation well and methods of forming a device structure with an isolation well. The structure comprises a first well of a first conductivity type in a semiconductor substrate, and a second well of a second conductivity type in the semiconductor substrate. The second conductivity type is opposite to the first conductivity type. The first well includes a plurality of segments, and the second well is positioned in a vertical direction between the segments of the first well and a top surface of the semiconductor substrate.

Abstract: An integrated circuit (IC) structure with a conductive pathway through resistive semiconductor material, e.g., for bipolar transistors, is provided. The IC structure may include a resistive semiconductor material having a first end coupled to a first doped semiconductor material. The first doped semiconductor material has a first doping type. A doped well may be coupled to a second end of the resistive semiconductor material. The doped well has a second doping type opposite the first doping type. A second doped semiconductor material is coupled to the doped well and has the first doping type. The resistive semiconductor material is within a conductive pathway from the first doped semiconductor material to the second doped semiconductor material.