Patents by Inventor Rajendran Sharma

Rajendran Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5633606
    Abstract: A scan flip-fop is designed to hold the state of the slave latch during scan shifting. This allows an ATPG tool to develop robust delay path tests using combinational scan flip-flop models. Combinational scan flip-flop models suffice because the launch can be done in the cycle before test enable goes active and capture can be performed during the cycle in which test enable is active. Thus, multiple clocks during the capture cycle are not necessary and, therefore, sequential delay path ATPG is not necessary. It is only necessary for the ATPG tool to store the last parallel vector in a buffer. The dynamic latch used for the scan slave latch is made small and slow, thereby increasing the delay along the data path during shifting, making the cell immune to hold time violation for any reasonable amount of clock skew.
    Type: Grant
    Filed: July 20, 1995
    Date of Patent: May 27, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Brian C. Gaudet, Rajendran Sharma, Ronald Pasqualini